aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts59
1 files changed, 36 insertions, 23 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts
index 0eb9e726a9b8..614b4ce330b1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts
@@ -123,40 +123,54 @@
/*
* Rename SoM signals according to board usage:
- * SPI_A_WP -> CAN_ADDR0
- * SPI_A_HOLD -> CAN_ADDR1
- * GPIO_B_0 -> DIO1_OUT
- * GPIO_B_1 -> DIO2_OUT
+ * GPIO_B_0 -> IO_EXP_INT
+ * GPIO_B_1 -> IO_EXP_RST
*/
&gpio3 {
gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5",
- "SDIO_B_D6", "SDIO_B_D7", "CAN_ADDR0", "CAN_ADDR1",
+ "SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD",
"UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1",
"SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4",
- "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "DIO1_OUT",
- "DIO2_OUT", "", "BOOT_SEL0", "BOOT_SEL1",
+ "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "IO_EXP_INT",
+ "IO_EXP_RST", "", "BOOT_SEL0", "BOOT_SEL1",
"", "", "SDIO_B_CD", "SDIO_B_PWR_EN",
"HDMI_CEC", "HDMI_HPD";
};
/*
- * Rename SoM signals according to board usage:
- * GPIO_B_5 -> DIO2_IN
- * GPIO_B_6 -> DIO3_IN
- * GPIO_B_7 -> DIO4_IN
- * GPIO_B_3 -> DIO4_OUT
- * GPIO_B_4 -> DIO1_IN
- * GPIO_B_2 -> DIO3_OUT
+ * Rename SoM signals according to board usage and remove labels for unsed pins:
+ * GPIO_A_6 -> TFT_RESET
+ * GPIO_A_7 -> TFT_STBY
+ * GPIO_B_3 -> CSI_ENABLE
+ * GPIO_B_2 -> USB_HUB_RST
*/
&gpio4 {
- gpio-line-names = "DIO2_IN", "DIO3_IN", "DIO4_IN", "GPIO_C_0",
+ gpio-line-names = "", "", "", "",
"ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",
"ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",
"ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",
- "ETH_A_TX_EN", "ETH_A_TX_CLK", "DIO4_OUT", "DIO1_IN",
- "DIO3_OUT", "GPIO_A_6", "CAN_A_TX", "UART_A_CTS",
+ "ETH_A_TX_EN", "ETH_A_TX_CLK", "CSI_ENABLE", "",
+ "USB_HUB_RST", "TFT_RESET", "CAN_A_TX", "UART_A_CTS",
"UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX",
- "GPIO_A_7", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";
+ "TFT_STBY", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";
+};
+
+/*
+ * Rename SoM signals according to board usage:
+ * SPI_A_SDI -> CAN_ADDR0
+ * SPI_A_SDO -> CAN_ADDR1
+ */
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio5>;
+ gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2",
+ "PWM_1", "PWM_0", "SPI_A_SCK", "CAN_ADDR1",
+ "CAN_ADDR0", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO",
+ "SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA",
+ "I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT",
+ "I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX",
+ "UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX",
+ "UART_B_RX", "UART_B_TX";
};
&hdmi_pvi {
@@ -236,8 +250,6 @@
};
&usb_dwc3_1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_hub>;
#address-cells = <1>;
#size-cells = <0>;
dr_mode = "host";
@@ -246,7 +258,7 @@
usb-hub@1 {
compatible = "usb424,2514";
reg = <1>;
- reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
};
};
@@ -297,9 +309,10 @@
>;
};
- pinctrl_usb_hub: usbhubgrp {
+ pinctrl_gpio5: gpio5grp {
fsl,pins = <
- MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x46
+ MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x46 /* CAN_ADR0 */
+ MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x46 /* CAN_ADR1 */
>;
};
};