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path: root/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c (follow)
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2017-03-29drm/amdgpu:use clear_ring to clr RBMonk Liu1-0/+1
In resume routine, we need clr RB prior to the ring test of engine, otherwise some engine hang duplicated during GPU reset. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu:alloc mqd backupMonk Liu1-0/+10
this is required for restoring the mqds after GPU reset. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu:use MACRO like other placesMonk Liu1-4/+2
Change-Id: Ica8f86577a50d817119de4b4fb95068dc72652a9 Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu:divide KCQ mqd init to sw and hwMonk Liu1-65/+42
sw part only invoked once during sw_init. hw part invoked during first drv load and resume later. that way we cannot alloc mqd in hw/resume, we only keep mqd allocted in sw_init routine. and hw_init routine only kmap and set it. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu:minor cleanupMonk Liu1-4/+1
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu:no need use sriov vf checksMonk Liu1-9/+4
We ultimately want to re-use this for bare metal, so no need to have vf checks in the KIQ code itself since kiq itself is currently only used in VF cases. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu:bo_free_kernel will set ptr to NULL if freedMonk Liu1-1/+0
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu:imple mqd soft ini/finiMonk Liu1-0/+52
this is for SRIOV fix: mqd soft init/fini will be invoked by sw_init to allocate BO for compute MQD resource, instead of original scheme that hw_init allocates MQD. because if hw_init allocates MQD, then resume will allocate MQD, and that lead to memory leak after driver recovered from hang. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/damdgpu:add new mqd member in ringMonk Liu1-0/+2
introduce a new mqd member in ring is for later usage. we need keep a clean version of MQD for the purpose of recovering compute rings from hang. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu:cg & pg shouldn't active on VF deviceMonk Liu1-0/+9
CG & PG function changes engine clock/gating, which is not appropriate for VF device, because one vf doesn't know the whole picture of engine's overall workload. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-16drm/amdgpu: fix warning on older gcc releasesArnd Bergmann1-2/+2
gcc-4.8 warns about '{0}' being used an an initializer for nested structures: drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function ‘gfx_v8_0_ring_emit_ce_meta_init’: drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:7263:2: warning: missing braces around initializer [-Wmissing-braces] } ce_payload = {0}; drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function ‘gfx_v8_0_ring_emit_de_meta_init’: drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:7290:2: warning: missing braces around initializer [-Wmissing-braces] } de_payload = {0}; Using an empty {} initializer however has the same effect and works on all versions. Fixes: acad2b2a7b70 ("drm/amdgpu:implement CE/DE meta-init routines") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-13drm/amdgpu: Initialize pipe priority order on graphic initializationozeng1-0/+8
Initialized PIPE_ORDER_TS0/1/2/3 field of SPI_ARB_PRIORITY register to 2. This set the pipe priority order to: 02 - HP3D, CS_H, GFX, CS_M, CS_L Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amd/amdgpu: remove the uncessary parameter for ib schedulerJunwei Zhang1-2/+2
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu:in cntx_ctrl we need insert meta-init for CE/DE(V2)Monk Liu1-1/+9
to support SRIOV preemption. v2: fix emit_frame_size Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu:implement CE/DE meta-init routinesMonk Liu1-0/+61
those package need to insert into ring buffer for SRIOV case. they are used to let CP do preemption. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu:add META_DATA struct for CSA/SRIOV v2Monk Liu1-0/+7
META-DATA is used in GFX cmd submit, we have two format suit for META-DATA-init, one is legacy and another is for chained-ib preempt, which is used in vulkan UMD. v2: drop use CP version number to judge if chain-ib supports or not, we wait for it mature Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: simplify allocation of scratch regsNils Wallménius1-6/+1
The scratch regs are sequential so there's no need to keep them in an array, we can just return the index of the first free register + the base register. Also change the array of bools for keeping track of the free regs to a bitfield. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu/gfx8: fix bugon.cocci warningsJulia Lawall1-2/+1
Use BUG_ON instead of a if condition followed by BUG. Generated by: scripts/coccinelle/misc/bugon.cocci Reviewed-by: Christian König <christian.koenig@amd.com> Reviewd-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> CC: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu/gfx8: implement emit_rreg/wreg functionXiangliang Yu1-0/+37
Implement emit_rreg/wreg function for kiq ring. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: add get clockgating_state method for gfx v8Huang Rui1-0/+40
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu/gfx8: add support kernel interface queue(KIQ)Xiangliang Yu1-2/+605
KIQ is queue-memory based initialization method: setup KIQ queue firstly, then send command to KIQ to setup other queues, without accessing registers. For virtualization, need KIQ to access virtual function registers when running on guest mode. V2: use amdgpu_bo_create/free_kernel to allocate BO. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: use same enter/exit safe mode for gfx_8.Rex Zhu1-94/+1
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: refine gfx_v8 pg code.Rex Zhu1-11/+12
move en/disable GFX CP/SMU_HS PG to function gfx_v8_0_set_powergating_state Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-06drm/amd/amdgpu: add Polaris12 support (v3)Junwei Zhang1-5/+26
v2: agd: squash in various fixes v3: agd: squash in: drm/amdgpu: remove unnecessary smc sk firmware for polaris12 Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-12-15drm/amdgpu: refine set clock gating for tonga/polarisRex Zhu1-43/+122
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-12-15drm/amdgpu: fix pg can't be disabled by PG mask.Rex Zhu1-5/+2
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-12-15drm/amdgpu: always initialize gfx pg for gfx_v8.0.Rex Zhu1-39/+32
v2: always init gfx pg for asics that can support. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-12-15drm/amdgpu: fix init save/restore list in gfx_v8.0Rex Zhu1-2/+6
set valid data to mmRLC_SRM_INDEX_CNTL_ADDRx/DATAx. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2016-12-15drm/amdgpu: fix enable_cp_power_gating in gfx_v8.0.Rex Zhu1-1/+1
the CP_PG_DISABLE bit was reversed. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2016-12-08drm/amd/amdgpu: Add debugfs support for reading GPRs (v2)Tom St Denis1-0/+25
Implemented for SGPRs for GFX v8 initially. (v2) cleanup minor whitespace and remove sanity check and addressing is in dwords not bytes Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-12-06drm/amdgpu: update golden setting of tongaHuang Rui1-0/+1
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-12-06drm/amdgpu: Don't touch GFX hw during HW finiXiangliang Yu1-0/+4
For SR-IOV client, driver shouldn't touch the GFX hw during HW fini, otherwise, gfx will fail to start after rebooting guest os. Signed-off-by: shaoyunl <Shaoyun.Liu@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-12-06drm/amdgpu: drop redundant vi_mqd defineXiangliang Yu1-263/+3
Vi_structs.h has defined vi_mqd, drop redundant vi_mqd define. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-12-06drm/amd/amdgpu: enable GUI idle INT after enabling CGCGArindam Nath1-9/+9
GUI idle interrupts should be enabled only after we have enabled coarse grain clock gating (CGCG). This prevents GFX engine generating idle interrupt even though CGCG is not completely enabled. Most of the time this goes un-noticed, but on some Stoney ASICs this results in GFX engine hang after system resumes from suspend. The issue is not particular to Stoney though and could have occured on any ASIC. The patch fixes this issue. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reported-by: Sunil Uttarwar <Sunil.Uttarwar1@amd.com> Signed-off-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2016-12-06drm/amdgpu/gfx8: move eop programming per queueAlex Deucher1-30/+19
It's per queue not per pipe. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu:impl vgt_flush for VI(V5)Monk Liu1-1/+14
when shadowing enabled, tesselation app will trigger vm fault because below three tesselation registers: VGT_TF_RING_SIZE__CI__VI, VGT_HS_OFFCHIP_PARAM__CI__VI, VGT_TF_MEMORY_BASE__CI__VI, need to be programed after vgt-flush. Tesselation picture vm fault disappeared after vgt-flush introduced. v2:implement vgt-flush for CI & SI. v3:move vgt flush inside of cntx_cntrl v4:count vgt flush in frame_size v5:squash in typo fix Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-11drm/amd/amdgpu : Fix NULL pointer comparisonRavikant B Sharma1-1/+1
Replace direct comparisons to NULL i.e. 'x == NULL' with '!x'. As per coding standard. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ravikant B Sharma <ravikant.s2@samsung.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-11drm/amd/amdgpu: Clean up wave gfx8 helperTom St Denis1-1/+5
De-numberify indirect register access for gfx v8. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-07Backmerge tag 'v4.9-rc4' into drm-nextDave Airlie1-1/+0
Linux 4.9-rc4 This is needed for nouveau development.
2016-10-28Merge tag 'topic/drm-misc-2016-10-27' of ↵Dave Airlie1-6/+6
git://anongit.freedesktop.org/git/drm-intel into drm-next Pull request already again to get the s/fence/dma_fence/ stuff in and allow everyone to resync. Otherwise really just misc stuff all over, and a new bridge driver. * tag 'topic/drm-misc-2016-10-27' of git://anongit.freedesktop.org/git/drm-intel: drm/bridge: fix platform_no_drv_owner.cocci warnings drm/bridge: fix semicolon.cocci warnings drm: Print some debug/error info during DP dual mode detect drm: mark drm_of_component_match_add dummy inline drm/bridge: add Silicon Image SiI8620 driver dt-bindings: add Silicon Image SiI8620 bridge bindings video: add header file for Mobile High-Definition Link (MHL) interface drm: convert DT component matching to component_match_add_release() dma-buf: Rename struct fence to dma_fence dma-buf/fence: add an lockdep_assert_held() drm/dp: Factor out helper to distinguish between branch and sink devices drm/edid: Only print the bad edid when aborting drm/msm: add missing header dependencies drm/msm/adreno: move function declarations to header file drm/i2c/tda998x: mark symbol static where possible doc: add missing docbook parameter for fence-array drm: RIP mode_config->rotation_property drm/msm/mdp5: Advertize 180 degree rotation drm/msm/mdp5: Use per-plane rotation property
2016-10-25drm/amd/amdgpu: Put in rest of wave fieldsTom St Denis1-0/+6
Add the rest of the basic SQ WAVE fields to finish off the implementation. Eventually, a separate interface will be needed for GPRs. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amd/amdgpu: re-factor debugfs wave readerTom St Denis1-0/+26
Move IP version specific code into a callback. Also add support for gfx7 devices. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amdgpu: rework IP block registration (v2)Alex Deucher1-1/+19
This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also stored the status information in the same structure. v2: split out spelling fix into a separate patch add a function to add IPs to the list Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amdgpu: move align_mask and nop into ring funcs as well (v2)Christian König1-6/+8
They are constant as well. v2: update uvd and vce phys ring structures as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amdgpu: move the ring type into the funcs structure (v2)Christian König1-7/+7
It's constant, so it doesn't make to much sense to keep it with the variable data. v2: update vce and uvd phys mode ring structures as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amdgpu: move IB and frame size directly into the engine descriptionChristian König1-40/+18
I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amdgpu: remove explicit NULL init for parse_csChristian König1-2/+0
sed -i "/\.parse_cs = NULL,/d" drivers/gpu/drm/amd/amdgpu/*.c That's just a leftover from radeon. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amdgpu: remove 128 NOP hack from vm_flush v2Christian König1-5/+1
With the padding raised to 256 DW that shouldn't be needed any more. v2: reduce estimation as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amdgpu: pad gfx and compute rings to 256 dwChristian König1-2/+2
The same as on windows to avoid further problems with CE/DE command submission overlaps. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amdgpu/gfx8: use cached raster config values in csb setupAlex Deucher1-28/+2
Simplify the code and properly set the csb for harvest values. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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