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path: root/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c (follow)
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2016-07-07drm/amdgpu/gfx8: clean up polaris11 PG enableAlex Deucher1-5/+13
Fix the logic for enabling/disabling. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu/gfx8: add powergating support for CZ/STAlex Deucher1-6/+126
This implements powergating support for CZ/ST asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu/gfx8: rename some pg functionsAlex Deucher1-10/+12
So they can be shared with other asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu/gfx8: add state setup for CZ/ST GFX power gatingAlex Deucher1-5/+128
This sets up the CP jump table and GDS buffer and sets the PG state registers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-06-29drm/amdgpu: add ACLK_CNTL setting for polaris10Ken Wang1-0/+3
This is a temporary workaround for early boards. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-06-21drm/amdgpu/gfx8: update golden setting for polaris10Rex Zhu1-1/+2
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-06-09drm/amdgpu: fix gfx8 ucode mem leakMonk Liu1-1/+21
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-06-09drm/amdgpu/iceland: Set SC_PA_RASTER_CONFIG according to different RB enabledKen Wang1-1/+5
fix the raster config setting for different iceland configs. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-18drm/amdgpu: update Polaris11 golden settingFlora Cui1-2/+3
Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-18drm/amdgpu: update Polaris10 golden settingFlora Cui1-0/+1
Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: fix TC cache flushingMarek Olšák1-0/+1
TC_WB_ACTION must be set according to the docs Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: move VM fields into jobChristian König1-4/+6
They are the same for all IBs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: move context switch handling into common code v2Christian König1-5/+4
It was a source of bugs to repeat that in each IP version. v2: rename parameter Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: move preamble IB handling into common codeChristian König1-4/+0
This fixes the handling which was completely broken when you ad more than one preamble IB. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amd/amdgpu: Add name field to amd_ip_funcs (v2)Tom St Denis1-0/+1
Add name that we can print out in kernel messages to aid in debugging. v2: drop DAL changes for upstream Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: fetch cu_info once at initAlex Deucher1-7/+4
Fetch this info once at init and just store the results for future requests. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amd: cleanup remaining spaces and tabs v2Christian König1-1/+1
This is the result of running the following commands: find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/[ \t]\+$//' {} \; find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/[ \t]\+$//' {} \; find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/ \+\t/\t/' {} \; find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/ \+\t/\t/' {} \; v2: drop changes to DAL and internal headers Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: keep vm in job instead of ib (v2)Monk Liu1-2/+2
ib.vm is a legacy way to get vm, after scheduler implemented vm should be get from job, and all ibs from one job share the same vm, no need to keep ib.vm just move vm field to job. this patch as well add job as paramter to ib_schedule so it can get vm from job->vm. v2: agd: sqaush in: drm/amdgpu: check if ring emit_vm_flush exists in vm flush No vm flush on engines that don't support VM. bug: https://bugs.freedesktop.org/show_bug.cgi?id=95195 Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amd/amdgpu: Drop print_status callbacks.Tom St Denis1-182/+0
First patch in series to move to user mode debug tools we're removing the print_status callbacks. These functions were unused at the moment anyway. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amd/amdgpu: fix 64-bit divisionSlava Grigorev1-2/+2
Signed-off-by: Slava Grigorev <slava.grigorev@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu: change ELM/BAF to Polaris10/Polaris11Flora Cui1-58/+58
Adjust to preferred code names. Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amd/amdgpu: add power gating init for BaffinEric Huang1-0/+39
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amd/amdgpu: add power gating initialization support for GFX8.0Eric Huang1-3/+350
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amd/amdgpu: add medium grain powergating support for BaffinEric Huang1-0/+95
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu: add GFX support for ELM/BAFFlora Cui1-4/+551
V2: use gfx_8_0_*.h instead of gfx_8_1_*.h v3: agd: integrate support for gfx info table Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu/gfx: rework fiji cg functions so they can be sharedAlex Deucher1-16/+202
They can be shared with other asics with minor modifications. Acked-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu/gfx: adjust gfx_v8_0_send_serdes_cmd for STAlex Deucher1-6/+17
Acked-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu/gfx8: rename send_serdes_cmdAlex Deucher1-7/+7
So it can be shared with CZ/ST. Acked-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu/gfx: add proper CG flags for fijiAlex Deucher1-34/+48
We were already enabling these CG features, this uses the standard interface for doing so. Acked-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu: use the ring name for debugfs (v2)Christian König1-1/+1
Instead of hard coding just another name in the ring code. v2: squash in Tom's rebase fix Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu: reduce the ring size for GFXChristian König1-2/+2
Those are way too large. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu: use max_dw in ring_initChristian König1-2/+2
Instead of specifying the total ring size calculate that from the maximum number of dw a submission can have and the number of concurrent submissions. This fixes UVD with 8 concurrent submissions or more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-18Merge branch 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie1-2/+4
into drm-next A few other misc cleanups and bug fixes for 4.6. Highlights: - unify endian handling in powerplay - powerplay fixes - fix a regression in 4.5 on boards with no display connectors - fence cleanups and locking fixes - whitespace cleanups and code refactoring in radeon * 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux: (35 commits) drm/amdgpu/gfx7: add MTYPE definition drm/amdgpu: removing BO_VAs shouldn't be interruptible drm/amd/powerplay: show uvd/vce power gate enablement for tonga. drm/amd/powerplay: show uvd/vce power gate info for fiji drm/amdgpu: use sched fence if possible drm/amdgpu: move ib.fence to job.fence drm/amdgpu: give a fence param to ib_free drm/amdgpu: include the right version of gmc header files for iceland drm/radeon: fix indentation. drm/amd/powerplay: add uvd/vce dpm enabling flag to fix the performance issue for CZ drm/amdgpu: switch back to 32bit hw fences v2 drm/amdgpu: remove amdgpu_fence_is_signaled drm/amdgpu: drop the extra fence range check v2 drm/amdgpu: signal fences directly in amdgpu_fence_process drm/amdgpu: cleanup amdgpu_fence_wait_empty v2 drm/amdgpu: keep all fences in an RCU protected array v2 drm/amdgpu: add number of hardware submissions to amdgpu_fence_driver_init_ring drm/amdgpu: RCU protected amd_sched_fence_release drm/amdgpu: RCU protected amdgpu_fence_release drm/amdgpu: merge amdgpu_fence_process and _activity ...
2016-03-17drm/amdgpu: move ib.fence to job.fenceMonk Liu1-0/+2
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-17drm/amdgpu: give a fence param to ib_freeMonk Liu1-2/+2
thus amdgpu_ib_free() can hook sched fence to SA manager in later patches. BTW: for amdgpu_free_job(), it should only fence_put() the fence of the last ib once, so fix it as well in this patch. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-17Merge branch 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie1-6/+25
into drm-next A few more fixes and cleanups for 4.6: - DCE code cleanups - HDP flush/invalidation fixes - GPUVM fixes - switch to drm_vblank_[on|off] - PX fixes - misc bug fixes * 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux: (50 commits) drm/amdgpu: split pipeline sync out of SDMA vm_flush() as well drm/amdgpu: Revert "add mutex for ba_va->valids/invalids" drm/amdgpu: Revert "add lock for interval tree in vm" drm/amdgpu: Revert "add spin lock to protect freed list in vm (v3)" drm/amdgpu: reserve the PD during unmap and remove drm/amdgpu: Fix two bugs in amdgpu_vm_bo_split_mapping drm/radeon: Don't drop DP 2.7 Ghz link setup on some cards. MAINTAINERS: update radeon entry to include amdgpu as well drm/amdgpu: disable runtime pm on PX laptops without dGPU power control drm/radeon: disable runtime pm on PX laptops without dGPU power control drm/amd/amdgpu: Fix indentation in do_set_base() (DCEv8) drm/amd/amdgpu: make afmt_init cleanup if alloc fails (DCEv8) drm/amd/amdgpu: Move config init flag to bottom of sw_init (DCEv8) drm/amd/amdgpu: Don't proceed into audio_fini if audio is disabled (DCEv8) drm/amd/amdgpu: Fix identation in do_set_base() (DCEv10) drm/amd/amdgpu: Make afmt_init cleanup if alloc fails (DCEv10) drm/amd/amdgpu: Move initialized flag to bottom of sw_init (DCEv10) drm/amd/amdgpu: Don't proceed in audio_fini if disabled (DCEv10) drm/amd/amdgpu: Fix indentation in dce_v11_0_crtc_do_set_base() drm/amd/amdgpu: Make afmt_init() cleanup if alloc fails (DCEv11) ...
2016-03-14Merge drm-fixes into drm-next.Dave Airlie1-2/+3
Nouveau wanted this to avoid some worse conflicts when I merge that.
2016-03-08drm/amdgpu: split pipeline sync and vm flushChristian König1-2/+9
This allows us to use the pipeline sync for other tasks as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2016-03-08drm/amdgpu: remove HW fence ownerChristian König1-4/+2
Not used any more since we now always use the sheduler. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2016-03-08drm/amdgpu: add hdp invalidation for gfx8Chunming Zhou1-0/+14
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-03drm/amdgpu: fix rb bitmap & cu bitmap calculationFlora Cui1-3/+6
Fix some copy paste typos. Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-02drm/amdgpu/gfx8: specify which engine to wait before vm flushChunming Zhou1-1/+2
Select between me and pfp properly. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-29drm/amdgpu: fix VM faults caused by vm_grab_id() v4Christian König1-4/+2
The owner must be per ring as long as we don't support sharing VMIDs per process. Also move the assigned VMID and page directory address into the IB structure. v3: assign the VMID to all IBs, not just the first one. v4: use correct pointer for owner Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-25drm/amdgpu/gfx: fix off by one in rb rework (v2)Alex Deucher1-5/+2
When I reworked this code, I messed up num rb count. v2: use hweight32 Reviewed-by: Ken Wang <Qingquing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-22drm/amdgpu/gfx8: fix priv reg interrupt enableAlex Deucher1-1/+1
Looks like a copy/paste typo. Reviewed-by: Christian König <christian.koenig@amd.com> Noticed-by: David Panariti <David.Panariti@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-12drm/amdgpu/vi: move uvd tiling config setup into uvd codeAlex Deucher1-12/+0
Split uvd and gfx programming. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-12drm/amdgpu/vi: move sdma tiling config setup into sdma codeAlex Deucher1-8/+0
Split sdma and gfx programming. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-12drm/amdgpu/gfx: clean up harvest configuration (v2)Alex Deucher1-91/+40
Read back harvest configuration from registers and simplify calculations. No need to program the raster config registers. These are programmed as golden registers and the user mode drivers program them as well. v2: rebase on Tom's patches Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-10drm/amdgpu: move sync into job objectChristian König1-2/+4
No need to keep that for every IB. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-10drm/amdgpu: send SDMA/GFX IB tests directly to the ring againChristian König1-6/+2
There is no point in sending them through the scheduler. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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