aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915 (follow)
AgeCommit message (Collapse)AuthorFilesLines
2025-09-03drm/i915/power: drop a couple of &i915->drm usagesJani Nikula1-6/+3
Switch from &i915->drm to display->drm. Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/20250902144929.3026700-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-09-03drm/i915/dp: convert open-coded timeout to poll_timeout_us()Jani Nikula1-8/+4
Use poll_timeout_us() instead of open-coding the timeout loop. Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250829113311.1930618-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-09-03drm/i915: Replace kmalloc() + copy_from_user() with memdup_user()Thorsten Blum1-9/+3
Replace kmalloc() followed by copy_from_user() with memdup_user() to improve and simplify set_context_image(), and to silence the following Coccinelle/coccicheck warning reported by memdup_user.cocci: WARNING opportunity for memdup_user No functional changes intended. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net> Link: https://lore.kernel.org/r/20250902081046.35463-2-thorsten.blum@linux.dev
2025-09-03drm/i915/display: Fix possible overflow on tc power domain selectionMika Kahola1-0/+3
There is a possibility that intel_encoder_to_tc() function returns negative i.e. TC_PORT_NONE (-1) value which may cause tc_port_power_domain() function to overflow. To fix this, let's add additional check that returns invalid power domain i.e. POWER_DOMAIN_INVALID in case tc port equals TC_PORT_NONE. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250829101226.4085757-1-mika.kahola@intel.com
2025-09-02drm/i915: compute pipe bpp from link bandwidth managementLee Shawn C8-36/+38
Since intel_fdi_compute_pipe_bpp() is no longer FDI-specific and now applies to all connectors. Move it to intel_link_bw.c, and rename to intel_link_bw_compute_pipe_bpp(). v2: Remove unused header file. Cc: Shankar Uma <uma.shankar@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com> [Imre: Remove unused intel_fdi.h include from intel_hdmi.c] Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250901055721.219995-3-shawn.c.lee@intel.com
2025-09-02drm/i915/hdmi: add debugfs to contorl HDMI bpcLee Shawn C3-10/+6
While performing HDMI compliance testing, test equipment may request different bpc output for signal measurement. However, display driver typically determines the maximum available bpc based on HW bandwidth. This change leverages the existing debugfs (intel_force_link_bpp) to manage HDMI bpc, and making it easier to pass HDMI CTS. v2: Using exist variable max_requested_bpc. v3: Extend intel_force_link_bpp to support HDMI as suggested by Imre. v4: Update commit message suggested by Jani. v5: Remove unused header file. Cc: Shankar Uma <uma.shankar@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250901055721.219995-2-shawn.c.lee@intel.com
2025-09-02drm/i915/hdcp: Remove the encoder check in hdcp enableSuraj Kandpal1-6/+0
Remove the intel_encoder NULL check from _intel_hdcp_enable. With all the changes it has gone through this check has become unnecessary since at this point the connector is supposed to have the encoder in it. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250819150729.88561-1-suraj.kandpal@intel.com
2025-09-02Merge tag 'drm-intel-gt-next-2025-09-01' of ↵Dave Airlie7-98/+98
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next Driver Changes: - Apply multiple JSL/EHL/Gen7/Gen6 workaround properly at context level (Sebastian) - Protect against overflow in active_engine() (Krzysztof) - Use try_cmpxchg64() in __active_lookup() (Uros) - Enable GuC CT_DEAD output in regular debug builds (John) - Static checker and style fixes (Sebastian) - Selftest improvements (Krzysztof) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://lore.kernel.org/r/aLWZoEZVlBj2d8J9@jlahtine-mobl
2025-08-27drm/i915/psr: Check PSR pause counter in __psr_wait_for_idle_lockedJouni Högander1-1/+1
PSR work is using __psr_wait_for_idle_locked to ensure PSR exit is completed before continuing to PSR activation. __psr_wait_for_idle_locked is unlocking PSR mutex which allows PSR disable/enable and PSR pause/resume while PSR idle is being wait. PSR enable status is already checked after locking again PSR mutex but PSR pause counter check is missing. Due to this PSR work may continue to PSR activation even PSR is paused. Fix this by checking PSR pause counter in __psr_wait_for_idle_locked after PSR mutex is locked again. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Jeevan B <jeevan.b@intel.com> Link: https://lore.kernel.org/r/20250826074457.1992524-1-jouni.hogander@intel.com
2025-08-26drm/i915/psr: Do not unnecessarily remove underrun on idle PSR WAJouni Högander1-2/+3
We are currently removing underrun on idle PSR WA even if it's not applied. Fix this by checking pkg_c_latency_used on PSR exit as well. Fixes: 9b1795e9b0ae ("drm/i915/psr: Underrun on idle PSR wa only when pkgc latency > delayed vblank") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://lore.kernel.org/r/20250822105846.1023631-1-jouni.hogander@intel.com
2025-08-25drm/i915/psr: Check drm_dp_dpcd_read return value on PSR dpcd initJouni Högander1-11/+21
Currently we are ignoriong drm_dp_dpcd_read return values when reading PSR and Panel Replay capability DPCD register. Rework intel_psr_dpcd a bit to take care of checking the return value. v2: use drm_dp_dpcd_read_data Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20250821045918.17757-1-jouni.hogander@intel.com
2025-08-25drm/i915/edp: eDP Data OverrrideSuraj Kandpal1-0/+19
We need override certain link rates in favour of the next available higher link rate. The Link rates that need to be overridden are indicated by a mask in VBT. To make sure these modes are skipped we don't add them in them in the sink rates array. --v2 -Update the link rates after we have a final set of link rates [Ankit] -Break this patch up [Ankit] -Optimize the assingment during loop [Ankit] --v3 -Add protection against broken VBTs [Jani] --v4 -Fix build errors -Create a seprate function to check if edp data override is selected and using the correct vbt --v5 -Use correct number to check the num of edp rates [Ankit] --v6 -No seprate function check if vbt is broken in the reject rate function [Jani] Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250821042653.269227-4-suraj.kandpal@intel.com
2025-08-25drm/i915/bios: Add function to check if edp data override is neededSuraj Kandpal2-0/+34
Add a function that helps identify if the rate provided needs to be overridden. For this we need a function that compares the rate provided and bitmask of rates provided in VBT. --v2 -Rename functions [Jani] -Return the mask instead of parsing it in function [Jani] -Move the declaration in header [Jani] --v3 -Change function name to depict what the function does [Ankit] --v4 -Lets not use hweight [Ankit] Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250821042653.269227-3-suraj.kandpal@intel.com
2025-08-25drm/i915/vbt: Add eDP Data rate overrride field in VBTSuraj Kandpal2-1/+21
Add edp_data_rate_override field VBT which gives us a mask of rates which needs to be skipped in favour of subsequent higher rate. --v2 -Rename vbt field [Jani] -Fix comment to 263+ [Jani] -Use BIT_U32 [Jani] -Fix the bits assignment in vbt [Jani] --v3 -Add a mask which represents all link rates [Ankit] Bspec: 20124 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250821042653.269227-2-suraj.kandpal@intel.com
2025-08-21drm/i915/psr: Check pause counter before continuing to PSR activationJouni Högander1-0/+3
Currently intel_psr_work is re-activating PSR even when pause_counter > 0 which is incorrect. Fix this by checking pause_counter before re-activating PSR. Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14822 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250815084534.1637030-4-jouni.hogander@intel.com
2025-08-21drm/i915/psr: Do not activate disabled PSR on irq_aux_errorJouni Högander1-1/+3
Currently intel_psr_work is continuing to activation of PSR which was just disabled when irq_aux_error == true. Fix this by skipping everything else than intel_psr_handle_irq in intel_psr_work when irq_aux_error == true. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250815084534.1637030-3-jouni.hogander@intel.com
2025-08-21drm/i915/psr: drm_WARN_ON when activating disabled PSRJouni Högander1-0/+2
Add drm_WARN_ON for scenario where PSR is activated while it is disabled. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250815084534.1637030-2-jouni.hogander@intel.com
2025-08-21drm/i915/backlight: Fix divide by 0 error in i9xx_set_backlightSuraj Kandpal1-1/+2
pwm_level_max maybe 0 we do throw a warning but move ahead with execution which may later cause a /0 error. --v2 -return if the warn_on gets hit [Jani] Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20250819160438.145734-1-suraj.kandpal@intel.com
2025-08-20drm/i915/psr: Underrun on idle PSR wa only when pkgc latency > delayed vblankJouni Högander3-6/+17
Underrun on idle PSR workaround (Wa_16025596647) is supposed to be applied only when pkg c latency > delayed vblank. Currently we are applying it always when other criterias are met. Fix this by adding new boolean flag which is supposed to be set when calculating watermark levels and pkgc latency > delayed vblank is detected. currently this scenario is blocked but might be added later. Due to this add also TODO comment into skl_max_wm_level_for_vblank. Bspec: 74151 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://lore.kernel.org/r/20250519075223.443266-1-jouni.hogander@intel.com
2025-08-19drm/i915/dram: move fsb_freq and mem_freq to dram infoJani Nikula4-29/+26
Store fsb_freq and mem_freq in dram info the same way we do for other memory info on later platforms for a slightly more unified approach. This allows us to remove fsb_freq, mem_freq and is_ddr3 members from struct drm_i915_private and struct xe_device. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/a38c4b105ba9098fa0b128cb86cd4eb63bcc27e8.1755511595.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-19drm/i915/dram: bypass fsb/mem freq detection on dg2 and no displayJani Nikula1-1/+4
Non-display now calls the intel_fsb_freq() and intel_mem_freq() functions, so we don't have to have the frequencies initialized for dg2 or non-display cases. This is in preparation for unifying the pre-gen9 handling in dram info. DG2 remains a special case as described in commit 5eb6bf0b44e7 ("drm/i915/dg2: Don't read DRAM info"). v2: Rebase Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/7bfed06d431354f3918ea73d43a2ec8ed9426a76.1755511595.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-19drm/i915/rps: use intel_fsb_freq() and intel_mem_freq()Jani Nikula1-3/+8
The rps init only happens once, so it's not important to use the cached versions, and we can drop the dependency on them. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/6f3b703f7cb5605bf139cbe27697c1d4ffe7e719.1755511595.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-19drm/i915/dram: add intel_mem_freq()Jani Nikula2-5/+13
Add a more generic intel_mem_freq() function instead of platform specific ones. Expose it for future use outside of intel_dram.c. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/602103b290a92ba26d581eeb595ba5e707eb5bc4.1755511595.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-19drm/i915/dram: add intel_fsb_freq() and use itJani Nikula4-7/+13
Add a more generic intel_fsb_freq() function instead of platform specific ones. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/c5b77311c5f64b7163c86a042b7d023c07a685e2.1755511595.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-19drm/i915/switcheroo: check for NULL before dereferencingJani Nikula1-2/+2
Both i915_switcheroo_set_state() and i915_switcheroo_can_switch() check for i915 == NULL. Commit d2e184f8e16a ("drm/i915/switcheroo: pass display to HAS_DISPLAY()") started dereferencing it before the NULL check. Fix it. Fixes: d2e184f8e16a ("drm/i915/switcheroo: pass display to HAS_DISPLAY()") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/r/202508160035.hmzuKiww-lkp@intel.com/ Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/20250818071605.2541523-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-19drm/i915/gt: Relocate compression repacking WA for JSL/EHLSebastian Brzezinka1-9/+11
CACHE_MODE_0 registers should be saved and restored as part of the context, not during engine reset. Move the related workaround (Disable Repacking for Compression) from rcs_engine_wa_init() to icl_ctx_workarounds_init() for Jasper Lake and Elkhart Lake platforms. This ensures the WA is applied during context initialisation. BSPEC: 11322 Fixes: 0ddae025ab6c ("drm/i915: Disable compression tricks on JSL") Closes: Fixes: 0ddae025ab6c ("drm/i915: Disable compression tricks on JSL") Signed-off-by: Sebastian Brzezinka <sebastian.brzezinka@intel.com> Cc: stable@vger.kernel.org # v6.13+ Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/4feaa24094e019e000ceb6011d8cd419b0361b3f.1754902406.git.sebastian.brzezinka@intel.com (cherry picked from commit c9932f0d604e4c8f2c6018e598a322acb43c68a2) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2025-08-19drm/i915: silence rpm wakeref asserts on GEN11_GU_MISC_IIR accessJani Nikula1-0/+4
Commit 8d9908e8fe9c ("drm/i915/display: remove small micro-optimizations in irq handling") not only removed the optimizations, it also enabled wakeref asserts for the GEN11_GU_MISC_IIR access. Silence the asserts by wrapping the access inside intel_display_rpm_assert_{block,unblock}(). Reported-by: "Jason A. Donenfeld" <Jason@zx2c4.com> Closes: https://lore.kernel.org/r/aG0tWkfmxWtxl_xc@zx2c4.com Fixes: 8d9908e8fe9c ("drm/i915/display: remove small micro-optimizations in irq handling") Cc: stable@vger.kernel.org # v6.13+ Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250805115656.832235-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit cbd3baeffbc08052ce7dc53f11bf5524b4411056) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2025-08-19drm/i915/dp: Set min_bpp limit to 30 in HDR modeChaitanya Kumar Borah3-9/+15
Update intel_dp_compute_config_limits() to use a minimum of 30 bits per pixel when the connector is in HDR mode (specifically, when EOTF is SMPTE ST2084), aligning with HDR display requirements. To support this, the function now takes a drm_connector_state instead of an intel_connector, and the required updates are made in all call sites, including MST handling. This ensures sufficient bitdepth for HDR content to avoid banding. If the required bandwidth for 30 bpp cannot be supported, the driver will either fall back to DSC or reject the mode during atomic check if DSC is not supported. Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250730055523.2214966-3-chaitanya.kumar.borah@intel.com
2025-08-19drm/i915/dp: Refactor intel_dp_in_hdr_mode() for broader reuseChaitanya Kumar Borah3-13/+14
The intel_dp_in_hdr_mode() helper was previously defined in intel_dp_aux_backlight.c but is generally useful beyond that context. Move the function to intel_dp.c and declare it in intel_dp.h to make it accessible to other DP-related code paths that need to check HDR metadata state. This is a pure refactor with no functional change and prepares for a follow-up patch that uses this helper. Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250730055523.2214966-2-chaitanya.kumar.borah@intel.com
2025-08-18drm/i915/gt: Relocate Gen6 context-specific workaroundSebastian Brzezinka1-3/+3
CACHE_MODE_0 register should be saved and restored as part of the context, not during engine reset. Move the related workaround (RC_OP_FLUSH_ENABLE) from rcs_engine_wa_init() to gen6_ctx_workarounds_init() for Gen6 platforms. This ensures the WA is applied during context initialisation. CM0_STC_EVICT_DISABLE_LRA_SNB is also Gen6-specific, but it does not stick when applied in context, so it remains in engine init. BSPEC: 11322 Signed-off-by: Sebastian Brzezinka <sebastian.brzezinka@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/f493bab389e51b2faf7c9a439724e9ea9ca04053.1754902406.git.sebastian.brzezinka@intel.com
2025-08-18drm/i915/gt: Relocate Gen7 context-specific workaroundsSebastian Brzezinka1-12/+11
CACHE_MODE_1 and CACHE_MODE_0 register should be saved and restored as part of the context, not during engine reset. Move the related workarounds (RC_OP_FLUSH_ENABLE, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE) from rcs_engine_wa_init() to gen7_ctx_workarounds_init() for Gen7 platforms. This ensures the WA is applied during context initialisation. BSPEC: 11322, 11323 Signed-off-by: Sebastian Brzezinka <sebastian.brzezinka@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/06cf152803ab0050e09c521ac2fc3637549860b3.1754902406.git.sebastian.brzezinka@intel.com
2025-08-18drm/i915/gt: Relocate compression repacking WA for JSL/EHLSebastian Brzezinka1-9/+11
CACHE_MODE_0 registers should be saved and restored as part of the context, not during engine reset. Move the related workaround (Disable Repacking for Compression) from rcs_engine_wa_init() to icl_ctx_workarounds_init() for Jasper Lake and Elkhart Lake platforms. This ensures the WA is applied during context initialisation. BSPEC: 11322 Fixes: 0ddae025ab6c ("drm/i915: Disable compression tricks on JSL") Closes: Fixes: 0ddae025ab6c ("drm/i915: Disable compression tricks on JSL") Signed-off-by: Sebastian Brzezinka <sebastian.brzezinka@intel.com> Cc: stable@vger.kernel.org # v6.13+ Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/4feaa24094e019e000ceb6011d8cd419b0361b3f.1754902406.git.sebastian.brzezinka@intel.com
2025-08-18drm/i915/icl+/tc: Convert AUX powered WARN to a debug messageImre Deak1-3/+3
The BIOS can leave the AUX power well enabled on an output, even if this isn't required (on platforms where the AUX power is only needed for an AUX access). This was observed at least on PTL. To avoid the WARN which would be triggered by this during the HW readout, convert the WARN to a debug message. Cc: stable@vger.kernel.org # v6.8+ Reported-by: Charlton Lin <charlton.lin@intel.com> Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250811080152.906216-6-imre.deak@intel.com (cherry picked from commit 6cb52cba474b2bec1a3018d3dbf75292059a29a1) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2025-08-18drm/i915/lnl+/tc: Use the cached max lane count valueImre Deak1-1/+5
Use the cached max lane count value on LNL+, to account for scenarios where this value is queried after the HW cleared the corresponding pin assignment value in the TCSS_DDI_STATUS register after the sink got disconnected. For consistency, follow-up changes will use the cached max lane count value on other platforms as well and will also cache the pin assignment value in a similar way. Cc: stable@vger.kernel.org # v6.8+ Reported-by: Charlton Lin <charlton.lin@intel.com> Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250811080152.906216-5-imre.deak@intel.com (cherry picked from commit afc4e84388079f4d5ba05271632b7a4d8d85165c) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2025-08-18drm/i915/lnl+/tc: Fix max lane count HW readoutImre Deak1-0/+9
On LNL+ for a disconnected sink the pin assignment value gets cleared by the HW/FW as soon as the sink gets disconnected, even if the PHY ownership got acquired already by the BIOS/driver (and hence the PHY itself is still connected and used by the display). During HW readout this can result in detecting the PHY's max lane count as 0 - matching the above cleared aka NONE pin assignment HW state. For a connected PHY the driver in general (outside of intel_tc.c) expects the max lane count value to be valid for the video mode enabled on the corresponding output (1, 2 or 4). Ensure this by setting the max lane count to 4 in this case. Note, that it doesn't matter if this lane count happened to be more than the max lane count with which the PHY got connected and enabled, since the only thing the driver can do with such an output - where the DP-alt sink is disconnected - is to disable the output. v2: Rebased on change reading out the pin configuration only if the PHY is connected. Cc: stable@vger.kernel.org # v6.8+ Reported-by: Charlton Lin <charlton.lin@intel.com> Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250811080152.906216-4-imre.deak@intel.com (cherry picked from commit 33cf70bc0fe760224f892bc1854a33665f27d482) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2025-08-18drm/i915/icl+/tc: Cache the max lane count valueImre Deak1-9/+48
The PHY's pin assignment value in the TCSS_DDI_STATUS register - as set by the HW/FW based on the connected DP-alt sink's TypeC/PD pin assignment negotiation - gets cleared by the HW/FW on LNL+ as soon as the sink gets disconnected, even if the PHY ownership got acquired already by the driver (and hence the PHY itself is still connected and used by the display). This is similar to how the PHY Ready flag gets cleared on LNL+ in the same register. To be able to query the max lane count value on LNL+ - which is based on the above pin assignment - at all times even after the sink gets disconnected, the max lane count must be determined and cached during the PHY's HW readout and connect sequences. Do that here, leaving the actual use of the cached value to a follow-up change. v2: Don't read out the pin configuration if the PHY is disconnected. Cc: stable@vger.kernel.org # v6.8+ Reported-by: Charlton Lin <charlton.lin@intel.com> Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250811080152.906216-3-imre.deak@intel.com (cherry picked from commit 3e32438fc406761f81b1928d210b3d2a5e7501a0) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2025-08-18drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sinkImre Deak1-6/+11
The TypeC PHY HW readout during driver loading and system resume determines which TypeC mode the PHY is in (legacy/DP-alt/TBT-alt) and whether the PHY is connected, based on the PHY's Owned and Ready flags. For the PHY to be in DP-alt or legacy mode and for the PHY to be in the connected state in these modes, both the Owned (set by the BIOS/driver) and the Ready (set by the HW) flags should be set. On ICL-MTL the HW kept the PHY's Ready flag set after the driver connected the PHY by acquiring the PHY ownership (by setting the Owned flag), until the driver disconnected the PHY by releasing the PHY ownership (by clearing the Owned flag). On LNL+ this has changed, in that the HW clears the Ready flag as soon as the sink gets disconnected, even if the PHY ownership was acquired already and hence the PHY is being used by the display. When inheriting the HW state from BIOS for a PHY connected in DP-alt mode on which the sink got disconnected - i.e. in a case where the sink was connected while BIOS/GOP was running and so the sink got enabled connecting the PHY, but the user disconnected the sink by the time the driver loaded - the PHY Owned but not Ready state must be accounted for on LNL+ according to the above. Do that by assuming on LNL+ that the PHY is connected in DP-alt mode whenever the PHY Owned flag is set, regardless of the PHY Ready flag. This fixes a problem on LNL+, where the PHY TypeC mode / connected state was detected incorrectly for a DP-alt sink, which got connected and then disconnected by the user in the above way. v2: Rename tc_phy_in_legacy_or_dp_alt_mode() to tc_phy_owned_by_display(). (Luca, Jani) Cc: Jani Nikula <jani.nikula@intel.com> Cc: stable@vger.kernel.org # v6.8+ Reported-by: Charlton Lin <charlton.lin@intel.com> Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> [Imre: Add one-liner function documentation for tc_phy_owned_by_display()] Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250811080152.906216-2-imre.deak@intel.com (cherry picked from commit 89f4b196ee4b056e0e8c179b247b29d4a71a4e7e) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2025-08-15drm/i915/bo: remove unnecessary includeJani Nikula1-1/+1
intel_bo.c doesn't need intel_display_types.h for anything. Remove. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/20250814132445.1573035-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-15drm/i915/audio: drop irq enabled check from LPE audio setupJani Nikula1-7/+4
There shouldn't be anything requiring irqs to be enabled at the point of LPE audio setup. Regardless, we've never hit the warning, as irqs are always enabled at the time LPE audio is initialized. Drop the superfluous warning, and the dependency on i915_drv.h. Fix style a bit while at it. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://lore.kernel.org/r/20250801122832.249985-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-15drm/i915/active: Use try_cmpxchg64() in __active_lookup()Uros Bizjak1-3/+2
Replace this pattern in __active_lookup(): cmpxchg64(*ptr, old, new) == old ... with the simpler and faster: try_cmpxchg64(*ptr, &old, new) The x86 CMPXCHG instruction returns success in the ZF flag, so this change saves a compare after the CMPXCHG. The patch also improves the explanation of what the code really does. cmpxchg64() will *succeed* for the winner of the race and try_cmpxchg64() nicely documents this fact. No functional change intended. Signed-off-by: Uros Bizjak <ubizjak@gmail.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tursulin@ursulin.net> Cc: David Airlie <airlied@gmail.com> Cc: Simona Vetter <simona@ffwll.ch> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net> Link: https://lore.kernel.org/r/20250814064326.95519-1-tvrtko.ursulin@igalia.com
2025-08-14drm/i915/display: drop __to_intel_display() usageJani Nikula4-20/+5
All the places that use __to_intel_display() now get passed a struct intel_display pointer, and the transitional adaptation macro has served its purpose. Remove the macro. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/d2c4a5aab3d69cec6f0640eed157a97531bd72f2.1754499175.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-14drm/i915/reg: separate VLV_DSPCLK_GATE_D from DSPCLK_GATE_DJani Nikula6-10/+10
All the places that use DSPCLK_GATE_D are specific to certain platforms, and the parametrization of it to support VLV/CHV MMIO display base isn't really buying us anything. Add a separate macro for VLV_DSPCLK_GATE_D and use it. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/ac16d9d5192595944bf9bcf70aa721b504bc90c0.1754499175.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-14drm/i915/gvt: convert mmio table to struct intel_displayJani Nikula1-132/+134
Underneath, the register macros really expect a struct intel_display. Switch to it in preparation for removing the transitional __to_intel_display() macro. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/ef50b08c9bf6066201c86dc7e0f08f008c7c47d5.1754499175.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-14drm/i915/uncore: pass display to HAS_FPGA_DBG_UNCLAIMED()Jani Nikula2-4/+7
Underneath, HAS_FPGA_DBG_UNCLAIMED() really expects struct intel_display. Switch to it in preparation for removing the transitional __to_intel_display() macro. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/e8cda779e192095dfa35d618f88bf7bfa526ac06.1754499175.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-14drm/i915/drv: pass display to HAS_DISPLAY()Jani Nikula1-7/+7
Underneath, HAS_DISPLAY() really expects a struct intel_display. Switch to it in preparation for removing the transitional __to_intel_display() macro. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/e1789e82d876eabef550abf537ca5dd2b71cbe6c.1754499175.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-14drm/i915/switcheroo: pass display to HAS_DISPLAY()Jani Nikula1-2/+4
Underneath, HAS_DISPLAY() really expects a struct intel_display. Switch to it in preparation for removing the transitional __to_intel_display() macro. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/c9828991eb8870c45271141bf0912880a3a65c44.1754499175.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-14drm/i915/gem: pass display to HAS_DISPLAY()Jani Nikula1-1/+2
Underneath, HAS_DISPLAY() really expects a struct intel_display. Switch to it in preparation for removing the transitional __to_intel_display() macro. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/79c87f75771a1d120cdd35dcfd6b380620ce99f1.1754499175.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-14drm/i915/gmch: pass display to DISPLAY_VER()Jani Nikula1-1/+2
Underneath, DISPLAY_VER() really expects struct intel_display. Switch to it in preparation for removing the transitional __to_intel_display() macro. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/1f951102b3d073fd58c5211f399750aa80b51548.1754499175.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-14drm/i915/dram: pass display to macros that expect displayJani Nikula1-2/+3
Underneath, the HAS_DISPLAY() and DISPLAY_VER() macros really expect struct intel_display. Switch to it in preparation for removing the transitional __to_intel_display() macro. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/ee8bba57924629f97945b9cf05727ae7c0dfb8fd.1754499175.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-08-14drm/i915/irq: pass display to macros that expect displayJani Nikula1-6/+7
Underneath, the HAS_PCH_NOP(), DISPLAY_VER(), HAS_FBC(), and HAS_HOTPLUG() macros really expect a struct intel_display. Switch to it in preparation for removing the transitional __to_intel_display() macro. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/de3302dd9ebc21226a9dadcbcdeeaf01e57186be.1754499175.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-01-04 04:05:54 +0000