From f365355e65ee619e3b7baeca69b46fd2c4a5ec68 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Thu, 20 Dec 2007 13:11:18 -0600 Subject: [POWERPC] pasemi: Implement NMI support Some PWRficient-based boards have a NMI button that's wired up to a GPIO as interrupt source. By configuring the openpic accordingly, these get delivered as a machine check with high priority, instead of as an external interrupt. The device tree contains a property "nmi-source" in the openpic node for these systems, and it's the (hwirq) source for the input. Also, for these interrupts, the IACK is read from another register than the regular (MCACK instead), but they are EOI'd as usual. So implement said function for the mpic driver. Finally, move a couple of external function defines to include/ instead of local under sysdev. Being able to mask/unmask and eoi directly saves us from setting up a dummy irq handler that will never be called. Signed-off-by: Olof Johansson --- arch/powerpc/sysdev/mpic.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'arch/powerpc/sysdev/mpic.c') diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index f74fe26b787e..5a9d8c141e60 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -83,6 +83,7 @@ static u32 mpic_infos[][MPIC_IDX_END] = { MPIC_CPU_WHOAMI, MPIC_CPU_INTACK, MPIC_CPU_EOI, + MPIC_CPU_MCACK, MPIC_IRQ_BASE, MPIC_IRQ_STRIDE, @@ -121,6 +122,7 @@ static u32 mpic_infos[][MPIC_IDX_END] = { TSI108_CPU_WHOAMI, TSI108_CPU_INTACK, TSI108_CPU_EOI, + TSI108_CPU_MCACK, TSI108_IRQ_BASE, TSI108_IRQ_STRIDE, @@ -1126,6 +1128,11 @@ struct mpic * __init mpic_alloc(struct device_node *node, mb(); } + if (flags & MPIC_ENABLE_MCK) + mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), + mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) + | MPIC_GREG_GCONF_MCK); + /* Read feature register, calculate num CPUs and, for non-ISU * MPICs, num sources as well. On ISU MPICs, sources are counted * as ISUs are added @@ -1438,13 +1445,13 @@ void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); } -unsigned int mpic_get_one_irq(struct mpic *mpic) +static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) { u32 src; - src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK); + src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); #ifdef DEBUG_LOW - DBG("%s: get_one_irq(): %d\n", mpic->name, src); + DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); #endif if (unlikely(src == mpic->spurious_vec)) { if (mpic->flags & MPIC_SPV_EOI) @@ -1462,6 +1469,11 @@ unsigned int mpic_get_one_irq(struct mpic *mpic) return irq_linear_revmap(mpic->irqhost, src); } +unsigned int mpic_get_one_irq(struct mpic *mpic) +{ + return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); +} + unsigned int mpic_get_irq(void) { struct mpic *mpic = mpic_primary; @@ -1471,6 +1483,14 @@ unsigned int mpic_get_irq(void) return mpic_get_one_irq(mpic); } +unsigned int mpic_get_mcirq(void) +{ + struct mpic *mpic = mpic_primary; + + BUG_ON(mpic == NULL); + + return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); +} #ifdef CONFIG_SMP void mpic_request_ipis(void) -- cgit v1.2.3 From d87bf3bed71375b141e95b5fdbac413ac4b65184 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Thu, 27 Dec 2007 22:16:29 -0600 Subject: [POWERPC] pasemi: Distribute interrupts evenly across cpus By default the OpenPIC on PWRficient will bias to one core (since that will improve changes of the other core being able to stay idle/powered down). However, this conflicts with most irq load balancing schemes, since setting an interrupt to be delivered to either core doesn't really result in the load being shared. It also doesn't work well with the soft irq disable feature of PPC, since EE will stay on until the first interrupt is taken while soft disabled. Set the gconf0 config bit that enables even distribution of interrupts among the two cores. Signed-off-by: Olof Johansson --- arch/powerpc/platforms/pasemi/setup.c | 2 +- arch/powerpc/sysdev/mpic.c | 5 +++++ include/asm-powerpc/mpic.h | 3 +++ 3 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/sysdev/mpic.c') diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c index eb271fded876..1940e678878e 100644 --- a/arch/powerpc/platforms/pasemi/setup.c +++ b/arch/powerpc/platforms/pasemi/setup.c @@ -224,7 +224,7 @@ static __init void pas_init_IRQ(void) openpic_addr = of_read_number(opprop, naddr); printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr); - mpic_flags = MPIC_PRIMARY | MPIC_LARGE_VECTORS; + mpic_flags = MPIC_PRIMARY | MPIC_LARGE_VECTORS | MPIC_NO_BIAS; nmiprop = of_get_property(mpic_node, "nmi-source", NULL); if (nmiprop) diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 5a9d8c141e60..f88ff09c4711 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -1279,6 +1279,11 @@ void __init mpic_init(struct mpic *mpic) mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | MPIC_GREG_GCONF_8259_PTHROU_DIS); + if (mpic->flags & MPIC_NO_BIAS) + mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), + mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) + | MPIC_GREG_GCONF_NO_BIAS); + /* Set current processor priority to 0 */ mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h index e7ac8109b6e7..943c5a3fac8a 100644 --- a/include/asm-powerpc/mpic.h +++ b/include/asm-powerpc/mpic.h @@ -22,6 +22,7 @@ #define MPIC_GREG_GLOBAL_CONF_0 0x00020 #define MPIC_GREG_GCONF_RESET 0x80000000 #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 +#define MPIC_GREG_GCONF_NO_BIAS 0x10000000 #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff #define MPIC_GREG_GCONF_MCK 0x08000000 #define MPIC_GREG_GLOBAL_CONF_1 0x00030 @@ -350,6 +351,8 @@ struct mpic #define MPIC_LARGE_VECTORS 0x00000100 /* Enable delivery of prio 15 interrupts as MCK instead of EE */ #define MPIC_ENABLE_MCK 0x00000200 +/* Disable bias among target selection, spread interrupts evenly */ +#define MPIC_NO_BIAS 0x00000400 /* MPIC HW modification ID */ #define MPIC_REGSET_MASK 0xf0000000 -- cgit v1.2.3