From 12e2b2d4c65f6164830e25fcd9624519a424b182 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 3 Jul 2019 16:20:42 -0400 Subject: drm/amd/display: add dcc programming for dual plane Add dual plane dcc programming support for surfaces. Removes unions from plane size and dcc params as they serve no practical purpose only making our code more convoluted. This results in easy dual plane dcc and surface size programming. Temporary diags_dm code is used to handle the interface change without breaking functionality as a diags change needs to be applied after this one. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index da89c2edb07c..7193acfcd779 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -149,7 +149,7 @@ struct mem_input_funcs { struct mem_input *mem_input, enum surface_pixel_format format, union dc_tiling_info *tiling_info, - union plane_size *plane_size, + struct plane_size *plane_size, enum dc_rotation_angle rotation, struct dc_plane_dcc_param *dcc, bool horizontal_mirror); -- cgit v1.2.3 From aa91916770d07cafafd24905b20e5350eb2dee30 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Fri, 26 Jul 2019 17:16:47 -0400 Subject: drm/amd/display: add dcn21 core DC changes Add missing parameters, to make dcn21 compile without errors Acked-by: Harry Wentland Signed-off-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 3 +++ drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 +++ drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 ++++ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 + 4 files changed, 11 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 42b6a6e41c0b..a82352a87808 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -385,6 +385,9 @@ struct dc_debug_options { struct dc_bw_validation_profile bw_val_profile; #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool disable_fec; +#endif +#ifdef CONFIG_DRM_AMD_DC_DCN2_1 + bool disable_48mhz_pwrdwn; #endif /* This forces a hard min on the DCFCLK requested to SMU/PP * watermarks are not affected. diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 8726bd7dd910..f189307750ab 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -87,6 +87,9 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); struct resource_pool; struct dc_state; struct resource_context; +#if defined(CONFIG_DRM_AMD_DC_DCN2_1) +struct clk_bw_params; +#endif struct resource_funcs { void (*destroy)(struct resource_pool **pool); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 7193acfcd779..e8668388581b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -40,6 +40,10 @@ struct cstate_pstate_watermarks_st { struct dcn_watermarks { uint32_t pte_meta_urgent_ns; uint32_t urgent_ns; +#if defined(CONFIG_DRM_AMD_DC_DCN2_1) + uint32_t frac_urg_bw_nom; + uint32_t frac_urg_bw_flip; +#endif struct cstate_pstate_watermarks_st cstate_pstate; }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 732a93df1844..3a938cd414ea 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -48,6 +48,7 @@ struct dce_hwseq_wa { bool DEGVIDCN10_253; bool false_optc_underflow; bool DEGVIDCN10_254; + bool DEGVIDCN21; }; struct hwseq_wa_state { -- cgit v1.2.3