From 08502cebee7c54d58fee0a54a98064dade4cc4de Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Wed, 20 Mar 2024 13:11:15 -0400 Subject: drm/amd/display: Add DCN401 dependant changes for DMCUB Update for DCN 4.0.1. Signed-off-by: Aurabindo Pillai Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 241 ++++++++++++++++++++++-- 1 file changed, 225 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h') diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index e85fd3ac52c7..bb4aed329393 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -150,10 +150,6 @@ #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) #endif -#if defined(__cplusplus) -extern "C" { -#endif - /** * OS/FW agnostic udelay */ @@ -487,10 +483,6 @@ struct dmub_visual_confirm_color { uint16_t panel_inst; }; -#if defined(__cplusplus) -} -#endif - //============================================================================== //================================================================= //============================================================================== @@ -1582,6 +1574,223 @@ struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; }; +struct dmub_flip_addr_info { + uint32_t surf_addr_lo; + uint32_t surf_addr_c_lo; + uint32_t meta_addr_lo; + uint32_t meta_addr_c_lo; + uint16_t surf_addr_hi; + uint16_t surf_addr_c_hi; + uint16_t meta_addr_hi; + uint16_t meta_addr_c_hi; +}; + +struct dmub_fams2_flip_info { + union { + struct { + uint8_t is_immediate: 1; + } bits; + uint8_t all; + } config; + uint8_t otg_inst; + uint8_t pipe_mask; + uint8_t pad; + struct dmub_flip_addr_info addr_info; +}; + +struct dmub_rb_cmd_fams2_flip { + struct dmub_cmd_header header; + struct dmub_fams2_flip_info flip_info; +}; + +struct dmub_optc_state_v2 { + uint32_t v_total_min; + uint32_t v_total_max; + uint32_t v_total_mid; + uint32_t v_total_mid_frame_num; + uint8_t program_manual_trigger; + uint8_t tg_inst; + uint8_t pad[2]; +}; + +struct dmub_optc_position { + uint32_t vpos; + uint32_t hpos; + uint32_t frame; +}; + +struct dmub_rb_cmd_fams2_drr_update { + struct dmub_cmd_header header; + struct dmub_optc_state_v2 dmub_optc_state_req; +}; + +/* HW and FW global configuration data for FAMS2 */ +/* FAMS2 types and structs */ +enum fams2_stream_type { + FAMS2_STREAM_TYPE_NONE = 0, + FAMS2_STREAM_TYPE_VBLANK = 1, + FAMS2_STREAM_TYPE_VACTIVE = 2, + FAMS2_STREAM_TYPE_DRR = 3, + FAMS2_STREAM_TYPE_SUBVP = 4, +}; + +/* dynamic stream state */ +struct dmub_fams2_legacy_stream_dynamic_state { + uint8_t force_allow_at_vblank; + uint8_t pad[3]; +}; + +struct dmub_fams2_subvp_stream_dynamic_state { + uint16_t viewport_start_hubp_vline; + uint16_t viewport_height_hubp_vlines; + uint16_t viewport_start_c_hubp_vline; + uint16_t viewport_height_c_hubp_vlines; + uint16_t phantom_viewport_height_hubp_vlines; + uint16_t phantom_viewport_height_c_hubp_vlines; + uint16_t microschedule_start_otg_vline; + uint16_t mall_start_otg_vline; + uint16_t mall_start_hubp_vline; + uint16_t mall_start_c_hubp_vline; + uint8_t force_allow_at_vblank_only; + uint8_t pad[3]; +}; + +struct dmub_fams2_drr_stream_dynamic_state { + uint16_t stretched_vtotal; + uint8_t use_cur_vtotal; + uint8_t pad; +}; + +struct dmub_fams2_stream_dynamic_state { + uint64_t ref_tick; + uint32_t cur_vtotal; + uint16_t adjusted_allow_end_otg_vline; + uint8_t pad[2]; + struct dmub_optc_position ref_otg_pos; + struct dmub_optc_position target_otg_pos; + union { + struct dmub_fams2_legacy_stream_dynamic_state legacy; + struct dmub_fams2_subvp_stream_dynamic_state subvp; + struct dmub_fams2_drr_stream_dynamic_state drr; + } sub_state; +}; + +/* static stream state */ +struct dmub_fams2_legacy_stream_static_state { + uint8_t vactive_det_fill_delay_otg_vlines; + uint8_t programming_delay_otg_vlines; +}; + +struct dmub_fams2_subvp_stream_static_state { + uint16_t vratio_numerator; + uint16_t vratio_denominator; + uint16_t phantom_vtotal; + uint16_t phantom_vactive; + union { + struct { + uint8_t is_multi_planar : 1; + uint8_t is_yuv420 : 1; + } bits; + uint8_t all; + } config; + uint8_t programming_delay_otg_vlines; + uint8_t prefetch_to_mall_otg_vlines; + uint8_t phantom_otg_inst; + uint8_t phantom_pipe_mask; + uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) +}; + +struct dmub_fams2_drr_stream_static_state { + uint16_t nom_stretched_vtotal; + uint8_t programming_delay_otg_vlines; + uint8_t only_stretch_if_required; + uint8_t pad[2]; +}; + +struct dmub_fams2_stream_static_state { + enum fams2_stream_type type; + uint32_t otg_vline_time_ns; + uint32_t otg_vline_time_ticks; + uint16_t htotal; + uint16_t vtotal; // nominal vtotal + uint16_t vblank_start; + uint16_t vblank_end; + uint16_t max_vtotal; + uint16_t allow_start_otg_vline; + uint16_t allow_end_otg_vline; + uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed + uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start + uint8_t contention_delay_otg_vlines; // time to budget for contention on execution + uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing + uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline + union { + struct { + uint8_t is_drr: 1; // stream is DRR enabled + uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal + uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank + } bits; + uint8_t all; + } config; + uint8_t otg_inst; + uint8_t pipe_mask; // pipe mask for the whole config + uint8_t num_planes; + uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) + uint8_t pad[DMUB_MAX_PLANES % 4]; + union { + struct dmub_fams2_legacy_stream_static_state legacy; + struct dmub_fams2_subvp_stream_static_state subvp; + struct dmub_fams2_drr_stream_static_state drr; + } sub_state; +}; + +/** + * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive + * p-state request to allow latency + */ +enum dmub_fams2_allow_delay_check_mode { + /* No check for request to allow delay */ + FAMS2_ALLOW_DELAY_CHECK_NONE = 0, + /* Check for request to allow delay */ + FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, + /* Check for prepare to allow delay */ + FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, +}; + +union dmub_fams2_global_feature_config { + struct { + uint32_t enable: 1; + uint32_t enable_ppt_check: 1; + uint32_t enable_stall_recovery: 1; + uint32_t enable_debug: 1; + uint32_t enable_offload_flip: 1; + uint32_t enable_visual_confirm: 1; + uint32_t allow_delay_check_mode: 2; + uint32_t reserved: 24; + } bits; + uint32_t all; +}; + +struct dmub_cmd_fams2_global_config { + uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin + uint32_t lock_wait_time_us; // time to forecast acquisition of lock + uint32_t num_streams; + union dmub_fams2_global_feature_config features; + uint8_t pad[3]; +}; + +union dmub_cmd_fams2_config { + struct dmub_cmd_fams2_global_config global; + struct dmub_fams2_stream_static_state stream; +}; + +/** + * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) + */ +struct dmub_rb_cmd_fams2 { + struct dmub_cmd_header header; + union dmub_cmd_fams2_config config; +}; + /** * enum dmub_cmd_idle_opt_type - Idle optimization command type. */ @@ -2263,6 +2472,9 @@ enum dmub_cmd_fams_type { * on (for any SubVP cases that use a DRR display) */ DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, + DMUB_CMD__FAMS2_CONFIG = 4, + DMUB_CMD__FAMS2_DRR_UPDATE = 5, + DMUB_CMD__FAMS2_FLIP = 6, }; /** @@ -3547,6 +3759,7 @@ enum hw_lock_client { * Replay is the client of HW Lock Manager. */ HW_LOCK_CLIENT_REPLAY = 4, + HW_LOCK_CLIENT_FAMS2 = 5, /** * Invalid client. */ @@ -4722,7 +4935,11 @@ union dmub_rb_cmd { * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. */ struct dmub_rb_cmd_assr_enable assr_enable; + struct dmub_rb_cmd_fams2 fams2_config; + + struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; + struct dmub_rb_cmd_fams2_flip fams2_flip; }; /** @@ -4759,10 +4976,6 @@ union dmub_rb_out_cmd { //< DMUB_RB>==================================================================== //============================================================================== -#if defined(__cplusplus) -extern "C" { -#endif - /** * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer */ @@ -5039,10 +5252,6 @@ static inline void dmub_rb_get_return_data(struct dmub_rb *rb, dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); } -#if defined(__cplusplus) -} -#endif - //============================================================================== //==================================================================== //============================================================================== -- cgit v1.2.3 From b0ce597bbf223cfe07524b86eba4f9a057aa1ac6 Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Sat, 13 Apr 2024 23:50:03 -0400 Subject: drm/amd/display: [FW Promotion] Release 0.0.214.0 - Adjust the dmub_fw_boot_options reserved bits to be correct Acked-by: Aurabindo Pillai Signed-off-by: Anthony Koo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h') diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index bb4aed329393..7a0574e6c129 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -655,7 +655,7 @@ union dmub_fw_boot_options { uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ uint32_t ips_disable: 3; /* options to disable ips support*/ uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ - uint32_t reserved : 9; /**< reserved */ + uint32_t reserved : 8; /**< reserved */ } bits; /**< boot bits */ uint32_t all; /**< 32-bit access to bits */ }; -- cgit v1.2.3 From 5419a2076de1dd9b0b4a191d0dd07de7c4fa7040 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Thu, 18 Apr 2024 09:51:36 -0400 Subject: drm/amd/display: Notify idle link detection through shared state [Why] We can hang in IPS2 checking DMCUB_SCRATCH0 for link detection state. [How] Replace the HW access with a check on the shared state bit. This will work the same way as the SCRATCH0 but won't require a wake in the case where link detection isn't required. Reviewed-by: Duncan Ma Acked-by: Wayne Lin Signed-off-by: Nicholas Kazlauskas Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 30 +++++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 10 +++++++++ drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 15 ++++++++++++- drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 ++ 5 files changed, 57 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 33d3307f5c1c..364ef9ae32f1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -1460,6 +1460,36 @@ void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_c dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D3); } +bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv) +{ + volatile const struct dmub_shared_state_ips_fw *ips_fw; + bool reallow_idle = false, should_detect = false; + + if (!dc_dmub_srv || !dc_dmub_srv->dmub) + return false; + + if (dc_dmub_srv->dmub->shared_state && + dc_dmub_srv->dmub->meta_info.feature_bits.bits.shared_state_link_detection) { + ips_fw = &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; + return ips_fw->signals.bits.detection_required; + } + + /* Detection may require reading scratch 0 - exit out of idle prior to the read. */ + if (dc_dmub_srv->idle_allowed) { + dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, false); + reallow_idle = true; + } + + should_detect = dmub_srv_should_detect(dc_dmub_srv->dmub); + + /* Re-enter idle if we're not about to immediately redetect links. */ + if (!should_detect && reallow_idle && dc_dmub_srv->idle_exit_counter == 0 && + !dc_dmub_srv->ctx->dc->debug.disable_dmub_reallow_idle) + dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, true); + + return should_detect; +} + void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle) { struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 3297c5b33265..580940222777 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -111,6 +111,16 @@ void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_ void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state powerState); +/** + * @dc_dmub_srv_should_detect() - Checks if link detection is required. + * + * While in idle power states we may need driver to manually redetect in + * the case of a missing hotplug. Should be called from a polling timer. + * + * Return: true if redetection is required. + */ +bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv); + /** * dc_wake_and_execute_dmub_cmd() - Wrapper for DMUB command execution. * diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index cec8aa1face5..cd51c91a822b 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -529,6 +529,7 @@ struct dmub_srv { uint32_t psp_version; /* Feature capabilities reported by fw */ + struct dmub_fw_meta_info meta_info; struct dmub_feature_caps feature_caps; struct dmub_visual_confirm_color visual_confirm_color; diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 7a0574e6c129..35096aa3d85b 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -496,6 +496,17 @@ struct dmub_visual_confirm_color { /* Offset from the end of the file to the dmub_fw_meta_info */ #define DMUB_FW_META_OFFSET 0x24 +/** + * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization + */ +union dmub_fw_meta_feature_bits { + struct { + uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ + uint32_t reserved : 31; + } bits; /**< status bits */ + uint32_t all; /**< 32-bit access to status bits */ +}; + /** * struct dmub_fw_meta_info - metadata associated with fw binary * @@ -521,6 +532,7 @@ struct dmub_fw_meta_info { uint32_t shared_state_size; /**< size of the shared state region in bytes */ uint16_t shared_state_features; /**< number of shared state features */ uint16_t reserved2; /**< padding bytes */ + union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ }; /** @@ -698,7 +710,8 @@ union dmub_shared_state_ips_fw_signals { uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ - uint32_t reserved_bits : 29; /**< Reversed */ + uint32_t detection_required : 1; /**< 1 if detection is required */ + uint32_t reserved_bits : 28; /**< Reversed */ } bits; uint32_t all; }; diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index 9bb4c51b1f5b..db16066bc893 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -510,6 +510,8 @@ enum dmub_status fw_info = dmub_get_fw_meta_info(params); if (fw_info) { + memcpy(&dmub->meta_info, fw_info, sizeof(*fw_info)); + fw_state_size = fw_info->fw_region_size; trace_buffer_size = fw_info->trace_buffer_size; -- cgit v1.2.3 From 36d1861725b2139b2d2e1b63fbe56222bc6a256e Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Sat, 27 Apr 2024 14:07:47 -0400 Subject: drm/amd/display: [FW Promotion] Release 0.0.216.0 - Implement command interface to query ABM SW algorithm and HW caps. This is primarily intended as a debugging interface - Add new definitions for max number of histogram bins and ABM curve segments available in hardware - Add structures to retrieve caps to describe ABM HW caps since not all ASICs have the same number of cure segments and bins Acked-by: Tom Chung Signed-off-by: Anthony Koo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 139 ++++++++++++++++++++++++ 1 file changed, 139 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h') diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 35096aa3d85b..abf248d46b1c 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -81,6 +81,16 @@ */ #define NUM_BL_CURVE_SEGS 16 +/** + * Maximum number of segments in ABM ACE curve. + */ +#define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 + +/** + * Maximum number of bins in ABM histogram. + */ +#define ABM_MAX_NUM_OF_HG_BINS 64 + /* Maximum number of SubVP streams */ #define DMUB_MAX_SUBVP_STREAMS 2 @@ -3865,6 +3875,82 @@ enum dmub_cmd_abm_type { * on restore we update state with passed in data. */ DMUB_CMD__ABM_SAVE_RESTORE = 7, + + /** + * Query ABM caps. + */ + DMUB_CMD__ABM_QUERY_CAPS = 8, +}; + +struct abm_ace_curve { + /** + * @offsets: ACE curve offsets. + */ + uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; + + /** + * @thresholds: ACE curve thresholds. + */ + uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; + + /** + * @slopes: ACE curve slopes. + */ + uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; +}; + +struct fixed_pt_format { + /** + * @sign_bit: Indicates whether one bit is reserved for the sign. + */ + bool sign_bit; + + /** + * @num_int_bits: Number of bits used for integer part. + */ + uint8_t num_int_bits; + + /** + * @num_frac_bits: Number of bits used for fractional part. + */ + uint8_t num_frac_bits; + + /** + * @pad: Explicit padding to 4 byte boundary. + */ + uint8_t pad; +}; + +struct abm_caps { + /** + * @num_hg_bins: Number of histogram bins. + */ + uint8_t num_hg_bins; + + /** + * @num_ace_segments: Number of ACE curve segments. + */ + uint8_t num_ace_segments; + + /** + * @pad: Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; + + /** + * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. + */ + struct fixed_pt_format ace_thresholds_format; + + /** + * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. + */ + struct fixed_pt_format ace_offsets_format; + + /** + * @ace_slopes_format: Format of the ACE slopes. + */ + struct fixed_pt_format ace_slopes_format; }; /** @@ -4274,6 +4360,54 @@ struct dmub_rb_cmd_abm_pause { struct dmub_cmd_abm_pause_data abm_pause_data; }; +/** + * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. + */ +struct dmub_cmd_abm_query_caps_in { + /** + * Panel instance. + */ + uint8_t panel_inst; + + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[3]; +}; + +/** + * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. + */ +struct dmub_cmd_abm_query_caps_out { + /** + * SW Algorithm caps. + */ + struct abm_caps sw_caps; + + /** + * ABM HW caps. + */ + struct abm_caps hw_caps; +}; + +/** + * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. + */ +struct dmub_rb_cmd_abm_query_caps { + /** + * Command header. + */ + struct dmub_cmd_header header; + + /** + * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. + */ + union { + struct dmub_cmd_abm_query_caps_in abm_query_caps_in; + struct dmub_cmd_abm_query_caps_out abm_query_caps_out; + } data; +}; + /** * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. */ @@ -4838,6 +4972,11 @@ union dmub_rb_cmd { */ struct dmub_rb_cmd_abm_save_restore abm_save_restore; + /** + * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. + */ + struct dmub_rb_cmd_abm_query_caps abm_query_caps; + /** * Definition of a DMUB_CMD__DP_AUX_ACCESS command. */ -- cgit v1.2.3 From c75bfd1567fec225b53574f5b7f392c4951de729 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Thu, 16 May 2024 10:30:53 -0400 Subject: drm/amd/display: Add new GPINT command definitions New commands for enabling copy of DC bounding box values from VBIOS DMUB Signed-off-by: Aurabindo Pillai Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 31 +++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h') diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index abf248d46b1c..f52716c54180 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -952,6 +952,37 @@ enum dmub_gpint_command { */ DMUB_GPINT__REPLAY_RESIDENCY = 14, + /** + * DESC: Copy bounding box to the host. + * ARGS: Version of bounding box to copy + * RETURN: Result of copying bounding box + */ + DMUB_GPINT__BB_COPY = 96, + + /** + * DESC: Updates the host addresses bit48~bit63 for bounding box. + * ARGS: The word3 for the 64 bit address + */ + DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, + + /** + * DESC: Updates the host addresses bit32~bit47 for bounding box. + * ARGS: The word2 for the 64 bit address + */ + DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, + + /** + * DESC: Updates the host addresses bit16~bit31 for bounding box. + * ARGS: The word1 for the 64 bit address + */ + DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, + + /** + * DESC: Updates the host addresses bit0~bit15 for bounding box. + * ARGS: The word0 for the 64 bit address + */ + DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, + /** * DESC: Updates the trace buffer lower 32-bit mask. * ARGS: The new mask -- cgit v1.2.3 From 1349db1581545a9e7253f74ccd9eabbcdf99b294 Mon Sep 17 00:00:00 2001 From: Chun-LiangChang Date: Fri, 10 May 2024 02:00:18 -0500 Subject: drm/amd/display: Add params of set_abm_event for VB Scaling [Why] Add parameters for set_abm_event to enable varibright scaling. VariBright Scaling is a feature to refer to system states like 1. Power mode 2. Battery Life percent 3. FullScreen video 4. Backlight slider to adjust variBright strength to get low power or user experience. [How] Add parameters of set_abm_event for VB Scaling Reviewed-by: Jun Lei Acked-by: Zaeem Mohamed Signed-off-by: Chun-LiangChang Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c | 18 ++++++++ drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h | 2 + drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 55 +++++++++++++++++++++++ 3 files changed, 75 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c index b851fc65f5b7..f4987e96fbf9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c @@ -297,3 +297,21 @@ bool dmub_abm_set_backlight_level(struct abm *abm, return true; } +bool dmub_abm_set_event(struct abm *abm, unsigned int scaling_enable, unsigned int scaling_strength_map, + unsigned int panel_inst) +{ + union dmub_rb_cmd cmd; + struct dc_context *dc = abm->ctx; + + memset(&cmd, 0, sizeof(cmd)); + cmd.abm_set_event.header.type = DMUB_CMD__ABM; + cmd.abm_set_event.header.sub_type = DMUB_CMD__ABM_SET_EVENT; + cmd.abm_set_event.abm_set_event_data.vb_scaling_enable = scaling_enable; + cmd.abm_set_event.abm_set_event_data.vb_scaling_strength_mapping = scaling_strength_map; + cmd.abm_set_event.abm_set_event_data.panel_mask = (1<