From 58d0d3e032b3679023afd0062d9ddfb7823c6e5d Mon Sep 17 00:00:00 2001 From: Mrinmay Sarkar Date: Tue, 30 Apr 2024 21:25:38 +0530 Subject: PCI: qcom-ep: Add support for SA8775P SOC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for SA8775P SoC to the Qualcomm PCIe Endpoint Controller driver. Adding new compatible string as it has different set of clocks compared to other SoCs. Link: https://lore.kernel.org/linux-pci/1714492540-15419-3-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Mrinmay Sarkar Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pci/controller/dwc/pcie-qcom-ep.c') diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 2fb8c15e7a91..a95c755df0fa 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -875,6 +875,7 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev) } static const struct of_device_id qcom_pcie_ep_match[] = { + { .compatible = "qcom,sa8775p-pcie-ep", }, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", }, { } -- cgit v1.2.3 From c94391ba52b9efa8797ad75a95c40c40df833c61 Mon Sep 17 00:00:00 2001 From: Mrinmay Sarkar Date: Mon, 18 Mar 2024 11:34:28 +0530 Subject: PCI: qcom-ep: Add HDMA support for SA8775P SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SA8775P SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP, so add support for it by passing the mapping format and the number of read/write channels count. The PCIe EP controller used on this SoC is of version 1.34.0, so a separate config struct is introduced for the sake of enabling HDMA conditionally. It should be noted that for the eDMA support (predecessor of HDMA), there are no mapping format and channels count specified. That is because eDMA supports auto detection of both parameters, whereas HDMA doesn't. [mani: reworded commit message, added kdoc, and minor cleanups] Link: https://lore.kernel.org/linux-pci/20240318-dw-hdma-v5-4-f04c5cdde760@linaro.org Signed-off-by: Mrinmay Sarkar Signed-off-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Reviewed-by: Frank Li Reviewed-by: Siddharth Vadapalli --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'drivers/pci/controller/dwc/pcie-qcom-ep.c') diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index a95c755df0fa..925a2427ece1 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -149,6 +149,14 @@ enum qcom_pcie_ep_link_status { QCOM_PCIE_EP_LINK_DOWN, }; +/** + * struct qcom_pcie_ep_cfg - Per SoC config struct + * @hdma_support: HDMA support on this SoC + */ +struct qcom_pcie_ep_cfg { + bool hdma_support; +}; + /** * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller * @pci: Designware PCIe controller struct @@ -803,6 +811,7 @@ static const struct dw_pcie_ep_ops pci_ep_ops = { static int qcom_pcie_ep_probe(struct platform_device *pdev) { + const struct qcom_pcie_ep_cfg *cfg; struct device *dev = &pdev->dev; struct qcom_pcie_ep *pcie_ep; char *name; @@ -816,6 +825,14 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) pcie_ep->pci.ops = &pci_ops; pcie_ep->pci.ep.ops = &pci_ep_ops; pcie_ep->pci.edma.nr_irqs = 1; + + cfg = of_device_get_match_data(dev); + if (cfg && cfg->hdma_support) { + pcie_ep->pci.edma.ll_wr_cnt = 8; + pcie_ep->pci.edma.ll_rd_cnt = 8; + pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE; + } + platform_set_drvdata(pdev, pcie_ep); ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); @@ -874,8 +891,12 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev) qcom_pcie_disable_resources(pcie_ep); } +static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { + .hdma_support = true, +}; + static const struct of_device_id qcom_pcie_ep_match[] = { - { .compatible = "qcom,sa8775p-pcie-ep", }, + { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", }, { } -- cgit v1.2.3 From c71b5eb3b86448aa4bad6b2ca94c6e1d1962a5fb Mon Sep 17 00:00:00 2001 From: Mrinmay Sarkar Date: Mon, 11 Mar 2024 19:41:36 +0530 Subject: PCI: qcom-ep: Override NO_SNOOP attribute for SA8775P EP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Due to some hardware changes, SA8775P has set the NO_SNOOP attribute in its TLP for all the PCIe controllers. NO_SNOOP attribute when set, the requester is indicating that no cache coherency issues exist for the addressed memory on the host i.e., memory is not cached. But in reality, requester cannot assume this unless there is a complete control/visibility over the addressed memory on the host. And worst case, if the memory is cached on the host, it may lead to memory corruption issues. It should be noted that the caching of memory on the host is not solely dependent on the NO_SNOOP attribute in TLP. So to avoid the corruption, this patch overrides the NO_SNOOP attribute by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not needed for other upstream supported platforms since they do not set NO_SNOOP attribute by default. Link: https://lore.kernel.org/linux-pci/1710166298-27144-3-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Mrinmay Sarkar Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'drivers/pci/controller/dwc/pcie-qcom-ep.c') diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 925a2427ece1..e2a28939b958 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -47,6 +47,7 @@ #define PARF_DBI_BASE_ADDR_HI 0x354 #define PARF_SLV_ADDR_SPACE_SIZE 0x358 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c +#define PARF_NO_SNOOP_OVERIDE 0x3d4 #define PARF_ATU_BASE_ADDR 0x634 #define PARF_ATU_BASE_ADDR_HI 0x638 #define PARF_SRIS_MODE 0x644 @@ -86,6 +87,10 @@ #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2) #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3) +/* PARF_NO_SNOOP_OVERIDE register fields */ +#define WR_NO_SNOOP_OVERIDE_EN BIT(1) +#define RD_NO_SNOOP_OVERIDE_EN BIT(3) + /* PARF_DEVICE_TYPE register fields */ #define PARF_DEVICE_TYPE_EP 0x0 @@ -152,9 +157,11 @@ enum qcom_pcie_ep_link_status { /** * struct qcom_pcie_ep_cfg - Per SoC config struct * @hdma_support: HDMA support on this SoC + * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping */ struct qcom_pcie_ep_cfg { bool hdma_support; + bool override_no_snoop; }; /** @@ -175,6 +182,7 @@ struct qcom_pcie_ep_cfg { * @num_clks: PCIe clocks count * @perst_en: Flag for PERST enable * @perst_sep_en: Flag for PERST separation enable + * @cfg: PCIe EP config struct * @link_status: PCIe Link status * @global_irq: Qualcomm PCIe specific Global IRQ * @perst_irq: PERST# IRQ @@ -202,6 +210,7 @@ struct qcom_pcie_ep { u32 perst_en; u32 perst_sep_en; + const struct qcom_pcie_ep_cfg *cfg; enum qcom_pcie_ep_link_status link_status; int global_irq; int perst_irq; @@ -497,6 +506,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) val |= BIT(8); writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); + if (pcie_ep->cfg && pcie_ep->cfg->override_no_snoop) + writel_relaxed(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN, + pcie_ep->parf + PARF_NO_SNOOP_OVERIDE); + return 0; err_disable_resources: @@ -811,7 +824,6 @@ static const struct dw_pcie_ep_ops pci_ep_ops = { static int qcom_pcie_ep_probe(struct platform_device *pdev) { - const struct qcom_pcie_ep_cfg *cfg; struct device *dev = &pdev->dev; struct qcom_pcie_ep *pcie_ep; char *name; @@ -826,8 +838,8 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) pcie_ep->pci.ep.ops = &pci_ep_ops; pcie_ep->pci.edma.nr_irqs = 1; - cfg = of_device_get_match_data(dev); - if (cfg && cfg->hdma_support) { + pcie_ep->cfg = of_device_get_match_data(dev); + if (pcie_ep->cfg && pcie_ep->cfg->hdma_support) { pcie_ep->pci.edma.ll_wr_cnt = 8; pcie_ep->pci.edma.ll_rd_cnt = 8; pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE; @@ -893,6 +905,7 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev) static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { .hdma_support = true, + .override_no_snoop = true, }; static const struct of_device_id qcom_pcie_ep_match[] = { -- cgit v1.2.3 From 912315715d7b74f7abdb6f063ebace44ee288af9 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 30 Apr 2024 11:43:42 +0530 Subject: PCI: qcom-ep: Disable resources unconditionally during PERST# assert MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All EP specific resources are enabled during PERST# deassert. As a counter operation, all resources should be disabled during PERST# assert. There is no point in skipping that if the link was not enabled. This will also result in enablement of the resources twice if PERST# got deasserted again. So remove the check from qcom_pcie_perst_assert() and disable all the resources unconditionally. Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver") Link: https://lore.kernel.org/linux-pci/20240430-pci-epf-rework-v4-1-22832d0d456f@linaro.org Tested-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'drivers/pci/controller/dwc/pcie-qcom-ep.c') diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index e2a28939b958..20c4a8063efb 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -521,12 +521,6 @@ err_disable_resources: static void qcom_pcie_perst_assert(struct dw_pcie *pci) { struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); - struct device *dev = pci->dev; - - if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) { - dev_dbg(dev, "Link is already disabled\n"); - return; - } dw_pcie_ep_cleanup(&pci->ep); qcom_pcie_disable_resources(pcie_ep); -- cgit v1.2.3