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authorDerrick Stolee <dstolee@microsoft.com>2018-08-20 18:24:24 +0000
committerJunio C Hamano <gitster@pobox.com>2018-08-21 10:22:50 -0700
commitb7758963424e238b9152f0c9991325ff7fdffff1 (patch)
tree51fd13feb648a9628f7ce108ee12b156658c1703 /diffcore-break.c
parentcommit-graph: update design document (diff)
downloadgit-b7758963424e238b9152f0c9991325ff7fdffff1.tar.gz
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test-repository: properly init repo
Signed-off-by: Derrick Stolee <dstolee@microsoft.com> Signed-off-by: Junio C Hamano <gitster@pobox.com>
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generated by cgit v1.2.3 (git 2.39.1) at 2025-12-16 22:47:19 +0000
e mode if length is aligned. This does not work in case of SPI slave mode where FIFO always needs to have data ready whenever master starts the clock. With DMA trigger size of 32 there will be a small window during slave TX where DMA is still putting data into FIFO but master would have started clock for next byte, resulting in shifting out of stale data. Similarly, on Slave RX side there may be RX FIFO overflow Fix this by setting FIFO watermark for DMA trigger to word length. This means DMA is triggered as soon as FIFO has space for word length bytes and DMA would make sure FIFO is almost always full therefore improving FIFO occupancy in both master and slave mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org> 2018-10-19spi: omap2-mcspi: Switch to readl_poll_timeout()Vignesh R1-13/+4 Use standard readl_poll_timeout() macro for polling on status bits. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org> 2018-10-19spi: spi-mem: add stm32 qspi controllerLudovic Barre3-0/+522 The qspi controller is a specialized communication interface targeting single, dual or quad SPI Flash memories (NOR/NAND). It can operate in any of the following modes: -indirect mode: all the operations are performed using the quadspi registers -read memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory tested on: -NOR: mx66l51235l -NAND: MT29F2G01ABAGD Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>