diff options
| author | E Shattow <e@freeshell.de> | 2025-05-02 03:30:41 -0700 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2025-05-15 21:08:27 +0100 |
| commit | 724a6718ce216f904192211f71973643f97384ec (patch) | |
| tree | a504f0a3c8dbca9df2e78485c53bc28aa67f982d | |
| parent | riscv: dts: starfive: jh7110-common: use macros for MMC0 pins (diff) | |
| download | linux-724a6718ce216f904192211f71973643f97384ec.tar.gz linux-724a6718ce216f904192211f71973643f97384ec.zip | |
riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by
boot loader before kernel.
Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index a2c72b385a90..cf1ee98454d6 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -354,9 +354,17 @@ }; &syscrg { - assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>, + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, + <&syscrg JH7110_SYSCLK_BUS_ROOT>, + <&syscrg JH7110_SYSCLK_PERH_ROOT>, + <&syscrg JH7110_SYSCLK_QSPI_REF>, + <&syscrg JH7110_SYSCLK_CPU_CORE>, <&pllclk JH7110_PLLCLK_PLL0_OUT>; - assigned-clock-rates = <500000000>, <1500000000>; + assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; + assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>; }; &sysgpio { |