diff options
| author | Luis de Arquer <luis.dearquer@inertim.com> | 2025-03-21 13:57:53 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2025-03-26 13:31:00 +0000 |
| commit | 7a874e8b54ea21094f7fd2d428b164394c6cb316 (patch) | |
| tree | 2343352c00afae47497972a2fb86b0575c8ebc7f | |
| parent | spi: dt-bindings: cdns,qspi-nor: Improve (diff) | |
| download | linux-7a874e8b54ea21094f7fd2d428b164394c6cb316.tar.gz linux-7a874e8b54ea21094f7fd2d428b164394c6cb316.zip | |
spi-rockchip: Fix register out of bounds access
Do not write native chip select stuff for GPIO chip selects.
GPIOs can be numbered much higher than native CS.
Also, it makes no sense.
Signed-off-by: Luis de Arquer <luis.dearquer@inertim.com>
Link: https://patch.msgid.link/365ccddfba110549202b3520f4401a6a936e82a8.camel@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | drivers/spi/spi-rockchip.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 1bc012fce7cb..1a6381de6f33 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -547,7 +547,7 @@ static int rockchip_spi_config(struct rockchip_spi *rs, cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; if (spi->mode & SPI_LSB_FIRST) cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; - if (spi->mode & SPI_CS_HIGH) + if ((spi->mode & SPI_CS_HIGH) && !(spi_get_csgpiod(spi, 0))) cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET; if (xfer->rx_buf && xfer->tx_buf) |