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| author | Likun Gao <Likun.Gao@amd.com> | 2019-01-04 14:13:09 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-03-19 15:03:57 -0500 |
| commit | 83e1ede637b3db6fca6f920a164e34eb8c552f8a (patch) | |
| tree | b11e7b8e1dd6bec18f02b2fef11f9a1ae48e3779 | |
| parent | drm/amd/powerplay: add function to get thermal range (diff) | |
| download | linux-83e1ede637b3db6fca6f920a164e34eb8c552f8a.tar.gz linux-83e1ede637b3db6fca6f920a164e34eb8c552f8a.zip | |
drm/amd/powerplay: add function to set thermal range
Add the function to set the correct min and max thermal value for smu11
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 630ba22431a5..cf6b203032f6 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -42,6 +42,8 @@ MODULE_FIRMWARE("amdgpu/vega20_smc.bin"); #define SMU11_TOOL_SIZE 0x19000 +#define SMU11_THERMAL_MINIMUM_ALERT_TEMP 0 +#define SMU11_THERMAL_MAXIMUM_ALERT_TEMP 255 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu, uint16_t msg) @@ -905,6 +907,36 @@ static int smu_v11_0_get_thermal_range(struct smu_context *smu, return 0; } +static int smu_v11_0_set_thermal_range(struct smu_context *smu, + struct PP_TemperatureRange *range) +{ + struct amdgpu_device *adev = smu->adev; + int low = SMU11_THERMAL_MINIMUM_ALERT_TEMP * + PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + int high = SMU11_THERMAL_MAXIMUM_ALERT_TEMP * + PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + uint32_t val; + + if (low < range->min) + low = range->min; + if (high > range->max) + high = range->max; + + if (low > high) + return -EINVAL; + + val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); + val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); + + WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); + + return 0; +} + static const struct smu_funcs smu_v11_0_funcs = { .init_microcode = smu_v11_0_init_microcode, .load_microcode = smu_v11_0_load_microcode, |