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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2026-01-06 13:13:19 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-01-09 12:12:39 +0100 |
| commit | a1b1ee0348f889ec262482e16e9ff670617db7b0 (patch) | |
| tree | e73830e9a3cfe2e8ed782d678afe62cd4e5f065c | |
| parent | 688fded2fc74b0539cd848b775418200c52a1fc2 (diff) | |
| download | linux-a1b1ee0348f889ec262482e16e9ff670617db7b0.tar.gz linux-a1b1ee0348f889ec262482e16e9ff670617db7b0.zip | |
arm64: dts: renesas: rzt2h-n2h-evk-common: Use GPIO for SD0 write protect
Switch SD0 write-protect detection to a GPIO on the RZ/T2H and RZ/N2H
EVKs. Both boards use a full-size SD card slot on the SD0 channel with
a dedicated WP pin.
The RZ/T2H and RZ/N2H SoCs use of_data_rcar_gen3, which sets
MMC_CAP2_NO_WRITE_PROTECT and causes the core to ignore the WP signal
unless a wp-gpios property is provided. Describe the WP pin as a GPIO
to allow the MMC core to evaluate the write-protect status correctly.
Fixes: d065453e5ee0 ("arm64: dts: renesas: rzt2h-rzn2h-evk: Enable SD card slot")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260106131319.643084-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 3eed1f3948e8..63bd91690b54 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -224,8 +224,7 @@ ctrl-pins { pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */ - <RZT2H_PORT_PINMUX(22, 5, 0x29)>, /* SD0_CD */ - <RZT2H_PORT_PINMUX(22, 6, 0x29)>; /* SD0_WP */ + <RZT2H_PORT_PINMUX(22, 5, 0x29)>; /* SD0_CD */ }; }; @@ -282,6 +281,7 @@ pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; vqmmc-supply = <&vqmmc_sdhi0>; + wp-gpios = <&pinctrl RZT2H_GPIO(22, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; sd-uhs-sdr50; sd-uhs-sdr104; |