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| author | Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> | 2025-09-04 14:52:25 +0800 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-09-16 14:31:23 -0500 |
| commit | b4f745f1d8adad62ba8c2065873c8a857ed4c3da (patch) | |
| tree | 82953244e645a5b7708b9621b9204b392c15d0a7 | |
| parent | arm64: dts: qcom: sm8450: enable camera clock controller by default (diff) | |
| download | linux-b4f745f1d8adad62ba8c2065873c8a857ed4c3da.tar.gz linux-b4f745f1d8adad62ba8c2065873c8a857ed4c3da.zip | |
arm64: dts: qcom: lemans: Add PCIe lane equalization preset properties
Add PCIe lane equalization preset properties with all values set to 5 for
8.0 GT/s and 16.0 GT/s data rates to enhance link stability.
Co-developed-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://lore.kernel.org/r/20250904065225.1762793-4-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/lemans.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 7e40f59e4aa3..4e6b42731d64 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -8327,6 +8327,9 @@ phys = <&pcie0_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + status = "disabled"; pcieport0: pcie@0 { @@ -8497,6 +8500,9 @@ phys = <&pcie1_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + status = "disabled"; pcie@0 { |