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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-01-25 21:25:02 -0800
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-01-25 21:25:02 -0800
commit8f5f90a872c38b4e78f3cc95e8a25434b98e4db2 (patch)
tree36c50b0c97286ab89c85016f7ab281f8e843c05c /arch/mips/pci/pci-ip27.c
parentstaging: comedi: addi_watchdog: all i/o registers are 32-bit (diff)
parentLinux 3.8-rc5 (diff)
downloadlinux-8f5f90a872c38b4e78f3cc95e8a25434b98e4db2.tar.gz
linux-8f5f90a872c38b4e78f3cc95e8a25434b98e4db2.zip
Merge 3.8-rc5 into staging-next
This resolves a merge issue with a iio driver, and the zram code. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/mips/pci/pci-ip27.c')
-rw-r--r--arch/mips/pci/pci-ip27.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index fdc24440294c..7f4f49b09b5b 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -143,7 +143,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
* A given PCI device, in general, should be able to intr any of the cpus
* on any one of the hubs connected to its xbow.
*/
-int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
return 0;
}
@@ -212,7 +212,7 @@ static inline void pci_enable_swapping(struct pci_dev *dev)
bridge->b_widget.w_tflush; /* Flush */
}
-static void __devinit pci_fixup_ioc3(struct pci_dev *d)
+static void pci_fixup_ioc3(struct pci_dev *d)
{
pci_disable_swapping(d);
}