diff options
| author | Atish Patra <atishp@rivosinc.com> | 2025-09-09 00:03:21 -0700 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-09-16 11:49:31 +0530 |
| commit | 656ef2ea30a90f910e1d2691674c98e5dcd164b5 (patch) | |
| tree | fc4b818c34a79ede6061c7297038dc2ac9c00548 /arch/riscv/include | |
| parent | drivers/perf: riscv: Add SBI v3.0 flag (diff) | |
| download | linux-656ef2ea30a90f910e1d2691674c98e5dcd164b5.tar.gz linux-656ef2ea30a90f910e1d2691674c98e5dcd164b5.zip | |
drivers/perf: riscv: Add raw event v2 support
SBI v3.0 introduced a new raw event type that allows wider
mhpmeventX width to be programmed via CFG_MATCH.
Use the raw event v2 if SBI v3.0 is available.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-2-d8f80cacb884@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/sbi.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 341e74238aa0..b0c41ef56968 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -161,7 +161,10 @@ struct riscv_pmu_snapshot_data { #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0) +/* SBI v3.0 allows extended hpmeventX width value */ +#define RISCV_PMU_RAW_EVENT_V2_MASK GENMASK_ULL(55, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 +#define RISCV_PMU_RAW_EVENT_V2_IDX 0x30000 #define RISCV_PLAT_FW_EVENT 0xFFFF /** General pmu event codes specified in SBI PMU extension */ @@ -219,6 +222,7 @@ enum sbi_pmu_event_type { SBI_PMU_EVENT_TYPE_HW = 0x0, SBI_PMU_EVENT_TYPE_CACHE = 0x1, SBI_PMU_EVENT_TYPE_RAW = 0x2, + SBI_PMU_EVENT_TYPE_RAW_V2 = 0x3, SBI_PMU_EVENT_TYPE_FW = 0xf, }; |