diff options
| author | Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> | 2025-08-28 16:39:26 +0530 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2025-09-01 12:47:07 +0200 |
| commit | ea7d792e11e10f502933c39f3836cb73d35dac36 (patch) | |
| tree | b0f3eadd902590e8a601eb5064cb283fe6026acc /arch/x86/kernel/apic/apic.c | |
| parent | x86/apic: Add support to send IPI for Secure AVIC (diff) | |
| download | linux-ea7d792e11e10f502933c39f3836cb73d35dac36.tar.gz linux-ea7d792e11e10f502933c39f3836cb73d35dac36.zip | |
x86/apic: Support LAPIC timer for Secure AVIC
Secure AVIC requires the LAPIC timer to be emulated by the hypervisor. KVM
already supports emulating the LAPIC timer using hrtimers. In order to emulate
it, APIC_LVTT, APIC_TMICT and APIC_TDCR register values need to be propagated
to the hypervisor for arming the timer. APIC_TMCCT register value has to be
read from the hypervisor, which is required for calibrating the APIC timer.
So, read/write all APIC timer registers from/to the hypervisor.
Co-developed-by: Kishon Vijay Abraham I <kvijayab@amd.com>
Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com>
Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tianyu Lan <tiala@microsoft.com>
Link: https://lore.kernel.org/20250828110926.208866-1-Neeraj.Upadhyay@amd.com
Diffstat (limited to 'arch/x86/kernel/apic/apic.c')
| -rw-r--r-- | arch/x86/kernel/apic/apic.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 7874284c1ca7..db18810576bc 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -592,6 +592,8 @@ static void setup_APIC_timer(void) 0xF, ~0UL); } else clockevents_register_device(levt); + + apic_update_vector(smp_processor_id(), LOCAL_TIMER_VECTOR, true); } /* |