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authorDave Jiang <dave.jiang@intel.com>2025-05-09 09:59:28 -0700
committerDave Jiang <dave.jiang@intel.com>2025-05-09 09:59:28 -0700
commit68d8b4f399e78a7be2bc69530c7e4b3e79fde9db (patch)
tree088e0048b0625c12705e1cd51ddc9f957d04cb08 /drivers/cxl/core/cdat.c
parentcxl/test: Address missing MODULE_DESCRIPTION warnings for cxl_test (diff)
parentcxl: Add a dev_dbg() when a decoder was added to a port (diff)
downloadlinux-68d8b4f399e78a7be2bc69530c7e4b3e79fde9db.tar.gz
linux-68d8b4f399e78a7be2bc69530c7e4b3e79fde9db.zip
Merge branch 'for-6.16/cxl-cleanups' into cxl-for-next
In preparation for code changes related to AMD Zen5 address translation support, a number of small code refactor and cleanups are send ahead.
Diffstat (limited to 'drivers/cxl/core/cdat.c')
-rw-r--r--drivers/cxl/core/cdat.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
index edb4f41eeacc..0ccef2f2a26a 100644
--- a/drivers/cxl/core/cdat.c
+++ b/drivers/cxl/core/cdat.c
@@ -28,7 +28,7 @@ static u32 cdat_normalize(u16 entry, u64 base, u8 type)
*/
if (entry == 0xffff || !entry)
return 0;
- else if (base > (UINT_MAX / (entry)))
+ if (base > (UINT_MAX / (entry)))
return 0;
/*