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authorDave Jiang <dave.jiang@intel.com>2025-05-23 13:26:24 -0700
committerDave Jiang <dave.jiang@intel.com>2025-05-23 13:26:24 -0700
commit9f153b7fb5ae45c7d426851f896487927f40e501 (patch)
treed7de5dd157f8e8a9fbead7c33a29054486f05351 /drivers/cxl/core/memdev.c
parentcxl/feature: Remove redundant code of get supported features (diff)
parentcxl/edac: Add CXL memory device soft PPR control feature (diff)
downloadlinux-9f153b7fb5ae45c7d426851f896487927f40e501.tar.gz
linux-9f153b7fb5ae45c7d426851f896487927f40e501.zip
Merge branch 'for-6.16/cxl-features-ras' into cxl-for-next
Add CXL RAS Features support. Features include "patrol scrub control", "error check scrub", "perform maintenance", and "memory sparing". This support connects the RAS Featurs to EDAC.
Diffstat (limited to 'drivers/cxl/core/memdev.c')
-rw-r--r--drivers/cxl/core/memdev.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
index ca9e38b222c8..f88a13adf7fa 100644
--- a/drivers/cxl/core/memdev.c
+++ b/drivers/cxl/core/memdev.c
@@ -27,6 +27,7 @@ static void cxl_memdev_release(struct device *dev)
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
ida_free(&cxl_memdev_ida, cxlmd->id);
+ devm_cxl_memdev_edac_release(cxlmd);
kfree(cxlmd);
}