diff options
| author | Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2021-05-19 10:47:22 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-06-04 16:03:26 -0400 |
| commit | 118a331516581c3acf1279857b0f663a54b7f31b (patch) | |
| tree | 6131f4a3a232dd54c1e194a68bbd9f22e237975b /drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | |
| parent | drm/amd/display: Add DCN3.1 yellow carp asic family IDs (diff) | |
| download | linux-118a331516581c3acf1279857b0f663a54b7f31b.tar.gz linux-118a331516581c3acf1279857b0f663a54b7f31b.zip | |
drm/amd/display: Add DCN3.1 clock manager support
Adds support for clock requests for the various parts of the DCN3.1 IP
and the interfaces and definitions for sending messages to SMU/PMFW.
Includes new support for z9/10, detecting SMU timeout and p-state
support enablement.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index dd52ebf56d62..2f413809f67b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -41,6 +41,9 @@ #include "dcn21/rn_clk_mgr.h" #include "dcn30/dcn30_clk_mgr.h" #include "dcn301/vg_clk_mgr.h" +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) +#include "dcn31/dcn31_clk_mgr.h" +#endif int clk_mgr_helper_get_active_display_cnt( @@ -261,6 +264,26 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p } break; #endif + +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) + case FAMILY_YELLOW_CARP: { + struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); + + if (clk_mgr == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) { + /* TODO: to add DCN31 clk_mgr support, once CLK IP header files are available, + * for now use DCN3.0 clk mgr. + */ + dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + return &clk_mgr->base.base; + } + return &clk_mgr->base.base; + } +#endif + default: ASSERT(0); /* Unknown Asic */ break; @@ -292,6 +315,13 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) vg_clk_mgr_destroy(clk_mgr); break; +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) + case FAMILY_YELLOW_CARP: + if (ASICREV_IS_YELLOW_CARP(clk_mgr_base->ctx->asic_id.hw_internal_rev)) + dcn31_clk_mgr_destroy(clk_mgr); + break; +#endif + default: break; } |