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| author | yi-lchen <yi-lchen@amd.com> | 2024-04-29 14:28:36 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-06-05 11:04:50 -0400 |
| commit | 975507d73c44e9382478d6fd2d49c5e660cca4f4 (patch) | |
| tree | d74313f49a61227d7d2407c6573de662ffdb3a3b /drivers/gpu/drm/amd/display/dc/inc/hw | |
| parent | Revert "drm/amdgpu/gfx11: enable gfx pipe1 hardware support" (diff) | |
| download | linux-975507d73c44e9382478d6fd2d49c5e660cca4f4.tar.gz linux-975507d73c44e9382478d6fd2d49c5e660cca4f4.zip | |
drm/amd/display: Keep VBios pixel rate div setting until next mode set
[why]
Vbios & Driver have difference pixel rate div policy.
When enabling fast boot & performing blank & unblank w/o timing setting,
pixel clock & pixel rate dividor are not match.
It would cause too high pixel reate and eDP would be black screen.
[How]
We would keep pixel rate div setting by Vbios until next timing setting.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: yi-lchen <yi-lchen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 867bc67aabfa..4fb1aacee894 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -176,6 +176,11 @@ struct dccg_funcs { enum pixel_rate_div k1, enum pixel_rate_div k2); + void (*get_pixel_rate_div)(struct dccg *dccg, + uint32_t otg_inst, + uint32_t *div_factor1, + uint32_t *div_factor2); + void (*set_valid_pixel_rate)( struct dccg *dccg, int ref_dtbclk_khz, |