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| author | Dave Airlie <airlied@redhat.com> | 2024-01-09 09:07:42 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2024-01-09 09:07:50 +1000 |
| commit | e54478fbdad20f2c58d0a4f99d01299ed8e7fe9c (patch) | |
| tree | a0e9b35d0cc755a26c6e6b2ae7aca864cc7dcad7 /drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h | |
| parent | Merge tag 'drm-misc-next-fixes-2024-01-04' of git://anongit.freedesktop.org/d... (diff) | |
| parent | drm/amd/display: Allow z8/z10 from driver (diff) | |
| download | linux-e54478fbdad20f2c58d0a4f99d01299ed8e7fe9c.tar.gz linux-e54478fbdad20f2c58d0a4f99d01299ed8e7fe9c.zip | |
Merge tag 'amd-drm-next-6.8-2024-01-05' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.8-2024-01-05:
amdgpu:
- VRR fixes
- PSR-SU fixes
- SubVP fixes
- DCN 3.5 fixes
- Documentation updates
- DMCUB fixes
- DML2 fixes
- UMC 12.0 updates
- GPUVM fix
- Misc code cleanups and whitespace cleanups
- DP MST fix
- Let KFD sync with GPUVM fences
- GFX11 reset fix
- SMU 13.0.6 fixes
- VSC fix for DP/eDP
- Navi12 display fix
- RN/CZN system aperture fix
- DCN 2.1 bandwidth validation fix
- DCN INIT cleanup
amdkfd:
- SVM fixes
- Revert TBA/TMA location change
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240105220522.4976-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h index bc96d0211360..813463ffe15c 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h @@ -417,6 +417,8 @@ struct integrated_info { /* V2.1 */ struct edp_info edp1_info; struct edp_info edp2_info; + uint32_t gpuclk_ss_percentage; + uint32_t gpuclk_ss_type; }; /* |