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| author | Sung Lee <sung.lee@amd.com> | 2020-03-30 17:19:01 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-04-22 18:11:47 -0400 |
| commit | f2cd2e5d861245dbf40e9b919e4734123164d8f4 (patch) | |
| tree | bc208ee153eee113cc64931bdc39798103f8f9b6 /drivers/gpu/drm/amd/display/modules/freesync/freesync.c | |
| parent | drm/amd/display: add optc get crc support for timings with ODM/DSC (diff) | |
| download | linux-f2cd2e5d861245dbf40e9b919e4734123164d8f4.tar.gz linux-f2cd2e5d861245dbf40e9b919e4734123164d8f4.zip | |
drm/amd/display: Set meta_chunk_value to 0 in DML if DCC disabled in DCN2.1
[WHY]:
Calculating refcyc_per_meta_chunk_vblank_l when DCC is disabled may lead
to a large number causing an assert to get hit. In VBA, this value is 0
when DCC is disabled.
[HOW]:
Set value to 0 to avoid hitting the assert.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c')
0 files changed, 0 insertions, 0 deletions