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authorJohn Smith <itistotalbotnet@gmail.com>2025-10-21 11:08:13 +0200
committerAlex Deucher <alexander.deucher@amd.com>2025-10-28 11:02:13 -0400
commit07a13f913c291d6ec72ee4fc848d13ecfdc0e705 (patch)
tree4eaced57802cfe8ed454d9f7594db95ce9c711cb /drivers/gpu/drm/amd/pm
parentdrm/amd/pm: fix smu table id bound check issue in smu_cmn_update_table() (diff)
downloadlinux-07a13f913c291d6ec72ee4fc848d13ecfdc0e705.tar.gz
linux-07a13f913c291d6ec72ee4fc848d13ecfdc0e705.zip
drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on Fiji
Previously this was initialized with zero which represented PCIe Gen 1.0 instead of using the maximum value from the speed table which is the behaviour of all other smumgr implementations. Fixes: 18edef19ea44 ("drm/amd/powerplay: implement fw image related smu interface for Fiji.") Signed-off-by: John Smith <itistotalbotnet@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit c52238c9fb414555c68340cd80e487d982c1921c)
Diffstat (limited to 'drivers/gpu/drm/amd/pm')
-rw-r--r--drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
index d2dbd90bb427..0a876c840c79 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
@@ -2024,7 +2024,7 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
table->VoltageResponseTime = 0;
table->PhaseResponseTime = 0;
table->MemoryThermThrottleEnable = 1;
- table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/
+ table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
table->PCIeGenInterval = 1;
table->VRConfig = 0;