diff options
| author | Kaustabh Chakraborty <kauschluss@disroot.org> | 2025-07-06 23:55:41 +0530 |
|---|---|---|
| committer | Inki Dae <inki.dae@samsung.com> | 2025-09-15 19:55:01 +0900 |
| commit | 9aa49c21aac071383353315036520ba753484c93 (patch) | |
| tree | 3d997e9b0ce5c1ba5cef41ec53a8505f8381568f /drivers/gpu/drm/bridge/samsung-dsim.c | |
| parent | drm/bridge: samsung-dsim: allow configuring the VIDEO_MODE bit (diff) | |
| download | linux-9aa49c21aac071383353315036520ba753484c93.tar.gz linux-9aa49c21aac071383353315036520ba753484c93.zip | |
drm/bridge: samsung-dsim: allow configuring PLL_M and PLL_S offsets
Currently, PLL_P offset of DSIM_PLLCTRL is configurable in the driver
data, while PLL_M and PLL_S offsets are hardcoded as 4-bit and 1-bit
offsets respectively, but Exynos7870's DSIM have them at 3-bit and 0-bit
offsets as per downstream kernel sources.
In order to support both, move both offset values to the driver data
struct and define it for every driver compatible. Reference the values
from there instead, in functions wherever required.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/bridge/samsung-dsim.c')
| -rw-r--r-- | drivers/gpu/drm/bridge/samsung-dsim.c | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index db154418e446..2884b3b7dc73 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -191,9 +191,7 @@ #define DSIM_PLL_DPDNSWAP_DAT (1 << 24) #define DSIM_FREQ_BAND(x) ((x) << 24) #define DSIM_PLL_EN BIT(23) -#define DSIM_PLL_P(x, offset) ((x) << (offset)) -#define DSIM_PLL_M(x) ((x) << 4) -#define DSIM_PLL_S(x) ((x) << 1) +#define DSIM_PLL(x, offset) ((x) << (offset)) /* DSIM_PHYCTRL */ #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) @@ -423,6 +421,8 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { .lane_esc_clk_bit = 19, .lane_esc_data_offset = 20, .pll_p_offset = 13, + .pll_m_offset = 4, + .pll_s_offset = 1, .main_vsa_offset = 22, .reg_values = reg_values, .pll_fin_min = 6, @@ -451,6 +451,8 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { .lane_esc_clk_bit = 19, .lane_esc_data_offset = 20, .pll_p_offset = 13, + .pll_m_offset = 4, + .pll_s_offset = 1, .main_vsa_offset = 22, .reg_values = reg_values, .pll_fin_min = 6, @@ -477,6 +479,8 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { .lane_esc_clk_bit = 19, .lane_esc_data_offset = 20, .pll_p_offset = 13, + .pll_m_offset = 4, + .pll_s_offset = 1, .main_vsa_offset = 22, .reg_values = reg_values, .pll_fin_min = 6, @@ -503,6 +507,8 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { .lane_esc_clk_bit = 19, .lane_esc_data_offset = 20, .pll_p_offset = 13, + .pll_m_offset = 4, + .pll_s_offset = 1, .main_vsa_offset = 22, .reg_values = exynos5433_reg_values, .pll_fin_min = 6, @@ -529,6 +535,8 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { .lane_esc_clk_bit = 19, .lane_esc_data_offset = 20, .pll_p_offset = 13, + .pll_m_offset = 4, + .pll_s_offset = 1, .main_vsa_offset = 22, .reg_values = exynos5422_reg_values, .pll_fin_min = 6, @@ -559,6 +567,8 @@ static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c */ .pll_p_offset = 14, + .pll_m_offset = 4, + .pll_s_offset = 1, .main_vsa_offset = 22, .reg_values = imx8mm_dsim_reg_values, .pll_fin_min = 2, @@ -710,8 +720,9 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, writel(driver_data->reg_values[PLL_TIMER], dsi->reg_base + driver_data->plltmr_reg); - reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | - DSIM_PLL_M(m) | DSIM_PLL_S(s); + reg = DSIM_PLL_EN | DSIM_PLL(p, driver_data->pll_p_offset) + | DSIM_PLL(m, driver_data->pll_m_offset) + | DSIM_PLL(s, driver_data->pll_s_offset); if (driver_data->has_freqband) { static const unsigned long freq_bands[] = { |