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| author | Simona Vetter <simona.vetter@ffwll.ch> | 2025-10-31 19:07:39 +0100 |
|---|---|---|
| committer | Simona Vetter <simona.vetter@ffwll.ch> | 2025-10-31 19:07:39 +0100 |
| commit | 3d8d35bf8dc8893e34d92212d413d7cfd89c560e (patch) | |
| tree | 0fbf0710a112181778f2f540fe2a397e7f8eb91c /drivers/gpu/drm/msm/msm_gpu.h | |
| parent | Merge tag 'amd-drm-fixes-6.18-2025-10-29' of https://gitlab.freedesktop.org/a... (diff) | |
| parent | drm/msm/dpu: Fix adjusted mode clock check for 3d merge (diff) | |
| download | linux-3d8d35bf8dc8893e34d92212d413d7cfd89c560e.tar.gz linux-3d8d35bf8dc8893e34d92212d413d7cfd89c560e.zip | |
Merge tag 'drm-msm-fixes-2025-10-29' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
Fixes for v6.18-rc4
CI
- Disable broken sanity job
GEM
- Fix vm_bind prealloc error path
- Fix dma-buf import free
- Fix last-fence update
- Reject MAP_NULL if PRR is unsupported
- Ensure vm is created in VM_BIND ioctl
GPU
- GMU fw parsing fix
DPU:
- Fixed mode_valid callback
- Fixed planes on DPU 1.x devices.
Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch>
From: Rob Clark <rob.clark@oss.qualcomm.com>
Link: https://patch.msgid.link/CACSVV03kUm1ms7FBg0m9U4ZcyickSWbnayAWqYqs0XH4UjWf+A@mail.gmail.com
Diffstat (limited to 'drivers/gpu/drm/msm/msm_gpu.h')
| -rw-r--r-- | drivers/gpu/drm/msm/msm_gpu.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index a597f2bee30b..2894fc118485 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -299,6 +299,17 @@ static inline struct msm_gpu *dev_to_gpu(struct device *dev) return container_of(adreno_smmu, struct msm_gpu, adreno_smmu); } +static inline bool +adreno_smmu_has_prr(struct msm_gpu *gpu) +{ + struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev); + + if (!adreno_smmu) + return false; + + return adreno_smmu && adreno_smmu->set_prr_addr; +} + /* It turns out that all targets use the same ringbuffer size */ #define MSM_GPU_RINGBUFFER_SZ SZ_32K #define MSM_GPU_RINGBUFFER_BLKSIZE 32 |