diff options
| author | Ben Skeggs <bskeggs@nvidia.com> | 2025-02-04 08:54:57 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2025-05-19 07:14:45 +1000 |
| commit | 284ad706ad2f50974d66dd1a22e985a5a4d329de (patch) | |
| tree | d3552a30ea61b9d6eaa99380e3000d2fba8a0bea /drivers/gpu/drm/nouveau/include | |
| parent | drm/nouveau/gsp: add hal for fifo.chan.doorbell_handle (diff) | |
| download | linux-284ad706ad2f50974d66dd1a22e985a5a4d329de.tar.gz linux-284ad706ad2f50974d66dd1a22e985a5a4d329de.zip | |
drm/nouveau: add support for GB20x
This commit adds support for the GB20x GPUs found on GeForce RTX 50xx
series boards.
Beyond a few miscellaneous register moves and HW class ID plumbing,
this reuses most of the code added to support GH100/GB10x.
Signed-off-by: Ben Skeggs <bskeggs@nvidia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timur Tabi <ttabi@nvidia.com>
Tested-by: Timur Tabi <ttabi@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/include')
8 files changed, 66 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvhw/ref/gb10b/dev_fbhub.h b/drivers/gpu/drm/nouveau/include/nvhw/ref/gb10b/dev_fbhub.h new file mode 100644 index 000000000000..4d0bb8e14298 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/ref/gb10b/dev_fbhub.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. + */ +#ifndef __gb10b_dev_fb_h__ +#define __gb10b_dev_fb_h__ + +#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO 0x008a1d58 /* RW-4R */ +#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */ +#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */ +#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xffffff00 /* RW--V */ +#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI 0x008a1d5c /* RW-4R */ +#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */ +#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */ +#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000fffff /* RW--V */ + +#endif // __gb10b_dev_fb_h__ + diff --git a/drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_ce.h b/drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_ce.h new file mode 100644 index 000000000000..b09f04b31738 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_ce.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. + */ +#ifndef __gb202_dev_ce_h__ +#define __gb202_dev_ce_h__ + +#define NV_CE_GRCE_MASK 0x001040d8 /* C--4R */ +#define NV_CE_GRCE_MASK_VALUE 9:0 /* C--VF */ +#define NV_CE_GRCE_MASK_VALUE_INIT 0x00f /* C---V */ + +#endif // __gb202_dev_ce_h__ diff --git a/drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_therm.h b/drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_therm.h new file mode 100644 index 000000000000..ed359cb528fb --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_therm.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. + */ +#ifndef __gb202_dev_therm_h__ +#define __gb202_dev_therm_h__ + +#define NV_THERM_I2CS_SCRATCH 0x00ad00bc /* RW-4R */ +#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */ +#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE NV_THERM_I2CS_SCRATCH +#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS 31:0 +#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS 0x000000FF +#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_FAILED 0x00000000 + +#endif // __gb202_dev_therm_h__ + diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 606483fc850b..ff6823cb2cd8 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -65,6 +65,7 @@ #define TURING_USERMODE_A 0x0000c461 #define AMPERE_USERMODE_A 0x0000c561 #define HOPPER_USERMODE_A 0x0000c661 +#define BLACKWELL_USERMODE_A 0x0000c761 #define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069 #define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369 @@ -89,6 +90,7 @@ #define AMPERE_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000c76f #define HOPPER_CHANNEL_GPFIFO_A 0x0000c86f #define BLACKWELL_CHANNEL_GPFIFO_A 0x0000c96f +#define BLACKWELL_CHANNEL_GPFIFO_B 0x0000ca6f #define NV50_DISP /* if0010.h */ 0x00005070 #define G82_DISP /* if0010.h */ 0x00008270 @@ -106,8 +108,10 @@ #define TU102_DISP /* if0010.h */ 0x0000c570 #define GA102_DISP /* if0010.h */ 0x0000c670 #define AD102_DISP /* if0010.h */ 0x0000c770 +#define GB202_DISP 0x0000ca70 #define GV100_DISP_CAPS 0x0000c373 +#define GB202_DISP_CAPS 0x0000ca73 #define NV31_MPEG 0x00003174 #define G82_MPEG 0x00008274 @@ -122,6 +126,7 @@ #define GV100_DISP_CURSOR /* if0014.h */ 0x0000c37a #define TU102_DISP_CURSOR /* if0014.h */ 0x0000c57a #define GA102_DISP_CURSOR /* if0014.h */ 0x0000c67a +#define GB202_DISP_CURSOR 0x0000ca7a #define NV50_DISP_OVERLAY /* if0014.h */ 0x0000507b #define G82_DISP_OVERLAY /* if0014.h */ 0x0000827b @@ -132,6 +137,7 @@ #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c37b #define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c57b #define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c67b +#define GB202_DISP_WINDOW_IMM_CHANNEL_DMA 0x0000ca7b #define NV50_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000507c #define G82_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000827c @@ -157,6 +163,7 @@ #define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d #define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d #define AD102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c77d +#define GB202_DISP_CORE_CHANNEL_DMA 0x0000ca7d #define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e #define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e @@ -168,6 +175,7 @@ #define GV100_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c37e #define TU102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c57e #define GA102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c67e +#define GB202_DISP_WINDOW_CHANNEL_DMA 0x0000ca7e #define NV50_TESLA 0x00005097 #define G82_TESLA 0x00008297 @@ -201,6 +209,7 @@ #define HOPPER_A 0x0000cb97 #define BLACKWELL_A 0x0000cd97 +#define BLACKWELL_B 0x0000ce97 #define NV74_BSP 0x000074b0 @@ -210,6 +219,7 @@ #define NVC7B0_VIDEO_DECODER 0x0000c7b0 #define NVC9B0_VIDEO_DECODER 0x0000c9b0 #define NVCDB0_VIDEO_DECODER 0x0000cdb0 +#define NVCFB0_VIDEO_DECODER 0x0000cfb0 #define GT212_MSVLD 0x000085b1 #define IGT21A_MSVLD 0x000086b1 @@ -240,10 +250,12 @@ #define AMPERE_DMA_COPY_B 0x0000c7b5 #define HOPPER_DMA_COPY_A 0x0000c8b5 #define BLACKWELL_DMA_COPY_A 0x0000c9b5 +#define BLACKWELL_DMA_COPY_B 0x0000cab5 #define NVC4B7_VIDEO_ENCODER 0x0000c4b7 #define NVC7B7_VIDEO_ENCODER 0x0000c7b7 #define NVC9B7_VIDEO_ENCODER 0x0000c9b7 +#define NVCFB7_VIDEO_ENCODER 0x0000cfb7 #define FERMI_DECOMPRESS 0x000090b8 @@ -264,6 +276,7 @@ #define ADA_COMPUTE_A 0x0000c9c0 #define HOPPER_COMPUTE_A 0x0000cbc0 #define BLACKWELL_COMPUTE_A 0x0000cdc0 +#define BLACKWELL_COMPUTE_B 0x0000cec0 #define NV74_CIPHER 0x000074c1 @@ -271,10 +284,12 @@ #define NVC4D1_VIDEO_NVJPG 0x0000c4d1 #define NVC9D1_VIDEO_NVJPG 0x0000c9d1 #define NVCDD1_VIDEO_NVJPG 0x0000cdd1 +#define NVCFD1_VIDEO_NVJPG 0x0000cfd1 #define NVB8FA_VIDEO_OFA 0x0000b8fa #define NVC6FA_VIDEO_OFA 0x0000c6fa #define NVC7FA_VIDEO_OFA 0x0000c7fa #define NVC9FA_VIDEO_OFA 0x0000c9fa #define NVCDFA_VIDEO_OFA 0x0000cdfa +#define NVCFFA_VIDEO_OFA 0x0000cffa #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index 0664195e5684..99579e7b9376 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -49,6 +49,7 @@ struct nvkm_device { GH100 = 0x180, AD100 = 0x190, GB10x = 0x1a0, + GB20x = 0x1b0, } card_type; u32 chipset; u8 chiprev; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h index 7bd73f9f749b..e0d777a933e1 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h @@ -104,6 +104,7 @@ int ga100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct n int ga102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); int gh100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); int gb100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gb202_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); #include <subdev/bios.h> #include <subdev/bios/ramcfg.h> diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fsp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fsp.h index 7122f814e4d0..8a3dbb1cbb46 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fsp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fsp.h @@ -20,4 +20,5 @@ int nvkm_fsp_boot_gsp_fmc(struct nvkm_fsp *, u64 args_addr, u32 rsvd_size, bool int gh100_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **); int gb100_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **); +int gb202_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h index c5982fd74725..226c7ec56b8e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h @@ -493,4 +493,5 @@ int ga102_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_ int gh100_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **); int ad102_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **); int gb100_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **); +int gb202_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **); #endif |