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| author | Karunika Choo <karunika.choo@arm.com> | 2025-08-07 17:26:32 +0100 |
|---|---|---|
| committer | Steven Price <steven.price@arm.com> | 2025-08-15 10:52:55 +0100 |
| commit | dd11c7dec74b0e125b75def169a53f3c86f35d6d (patch) | |
| tree | 4f39fa6daae428b8b6f51de55dd8569c43a40b7c /drivers/gpu/drm/panthor | |
| parent | drm/panthor: Serialize GPU cache flush operations (diff) | |
| download | linux-dd11c7dec74b0e125b75def169a53f3c86f35d6d.tar.gz linux-dd11c7dec74b0e125b75def169a53f3c86f35d6d.zip | |
drm/panthor: Make MMU cache maintenance use FLUSH_CACHES command
As the FLUSH_MEM and FLUSH_PT MMU_AS commands are deprecated in GPUs
from Mali-Gx20 onwards, this patch adds support for performing cache
maintenance via the FLUSH_CACHES command in GPU_COMMAND in place of
FLUSH_MEM and FLUSH_PT commands.
Mali-Gx10 and Mali-Gx15 GPUs also has support for the FLUSH_CACHES
command and will also use this by default going forward.
Reviewed-by: Steven Price <steven.price@arm.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Karunika Choo <karunika.choo@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20250807162633.3666310-7-karunika.choo@arm.com
Diffstat (limited to 'drivers/gpu/drm/panthor')
| -rw-r--r-- | drivers/gpu/drm/panthor/panthor_mmu.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/panthor/panthor_mmu.c index 4140f697ba5a..367c89aca558 100644 --- a/drivers/gpu/drm/panthor/panthor_mmu.c +++ b/drivers/gpu/drm/panthor/panthor_mmu.c @@ -29,6 +29,7 @@ #include "panthor_device.h" #include "panthor_gem.h" +#include "panthor_gpu.h" #include "panthor_heap.h" #include "panthor_mmu.h" #include "panthor_regs.h" @@ -568,6 +569,35 @@ static void lock_region(struct panthor_device *ptdev, u32 as_nr, write_cmd(ptdev, as_nr, AS_COMMAND_LOCK); } +static int mmu_hw_do_flush_on_gpu_ctrl(struct panthor_device *ptdev, int as_nr, + u32 op) +{ + const u32 l2_flush_op = CACHE_CLEAN | CACHE_INV; + u32 lsc_flush_op = 0; + int ret; + + if (op == AS_COMMAND_FLUSH_MEM) + lsc_flush_op = CACHE_CLEAN | CACHE_INV; + + ret = wait_ready(ptdev, as_nr); + if (ret) + return ret; + + ret = panthor_gpu_flush_caches(ptdev, l2_flush_op, lsc_flush_op, 0); + if (ret) + return ret; + + /* + * Explicitly unlock the region as the AS is not unlocked automatically + * at the end of the GPU_CONTROL cache flush command, unlike + * AS_COMMAND_FLUSH_MEM or AS_COMMAND_FLUSH_PT. + */ + write_cmd(ptdev, as_nr, AS_COMMAND_UNLOCK); + + /* Wait for the unlock command to complete */ + return wait_ready(ptdev, as_nr); +} + static int mmu_hw_do_operation_locked(struct panthor_device *ptdev, int as_nr, u64 iova, u64 size, u32 op) { @@ -585,6 +615,9 @@ static int mmu_hw_do_operation_locked(struct panthor_device *ptdev, int as_nr, if (op != AS_COMMAND_UNLOCK) lock_region(ptdev, as_nr, iova, size); + if (op == AS_COMMAND_FLUSH_MEM || op == AS_COMMAND_FLUSH_PT) + return mmu_hw_do_flush_on_gpu_ctrl(ptdev, as_nr, op); + /* Run the MMU operation */ write_cmd(ptdev, as_nr, op); |