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authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>2019-08-26 15:04:18 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-09-17 08:06:54 -0500
commita14e9e0292e29939ef078ab7f5a337edcd796ca1 (patch)
tree463ae10ce1c1ac391b8f89f839438707d66e418b /drivers/gpu/drm
parentdrm/amd/display: Add debugfs entry to force YUV420 output (diff)
downloadlinux-a14e9e0292e29939ef078ab7f5a337edcd796ca1.tar.gz
linux-a14e9e0292e29939ef078ab7f5a337edcd796ca1.zip
drm/amd/display: add vtg update after global sync update
Global sync update was missing vtg update resulting in underflow if vstartup decreased a significant amount. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index faaf8841c61e..4bb5ad19c4cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1361,7 +1361,7 @@ static void dcn20_program_pipe(
&& !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
dc->hwss.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
- if (pipe_ctx->update_flags.bits.global_sync)
+ if (pipe_ctx->update_flags.bits.global_sync) {
pipe_ctx->stream_res.tg->funcs->program_global_sync(
pipe_ctx->stream_res.tg,
pipe_ctx->pipe_dlg_param.vready_offset,
@@ -1369,6 +1369,10 @@ static void dcn20_program_pipe(
pipe_ctx->pipe_dlg_param.vupdate_offset,
pipe_ctx->pipe_dlg_param.vupdate_width);
+ pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+ pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+ }
+
if (pipe_ctx->update_flags.bits.odm)
dc->hwss.update_odm(dc, context, pipe_ctx);