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| author | Alexandru Ardelean <aardelean@baylibre.com> | 2024-09-19 16:04:43 +0300 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2024-10-05 12:09:06 +0100 |
| commit | f3838e934dfff284b84bd563e92cd60e7dda0cb8 (patch) | |
| tree | b4bcfde8517c187ed9619f3e4972c09fc4abc670 /drivers/iio/adc/ad7606.h | |
| parent | dt-bindings: iio: adc: add docs for AD7606C-{16,18} parts (diff) | |
| download | linux-f3838e934dfff284b84bd563e92cd60e7dda0cb8.tar.gz linux-f3838e934dfff284b84bd563e92cd60e7dda0cb8.zip | |
iio: adc: ad7606: add support for AD7606C-{16,18} parts
The AD7606C-16 and AD7606C-18 are pretty similar with the AD7606B.
The main difference between AD7606C-16 & AD7606C-18 is the precision in
bits (16 vs 18).
Because of that, some scales need to be defined for the 18-bit variants, as
they need to be computed against 2**18 (vs 2**16 for the 16 bit-variants).
Because the AD7606C-16,18 also supports bipolar & differential channels,
for SW-mode, the default range of 10 V or ±10V should be set at probe.
On reset, the default range (in the registers) is set to value 0x3 which
corresponds to '±10 V single-ended range', regardless of bipolar or
differential configuration.
Aside from the scale/ranges, the AD7606C-16 is similar to the AD7606B.
The AD7606C-18 variant offers 18-bit precision. Because of this, the
requirement to use this chip is that the SPI controller supports padding
of 18-bit sequences to 32-bit arrays.
Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606c-16.pdf
Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606c-18.pdf
Signed-off-by: Alexandru Ardelean <aardelean@baylibre.com>
Link: https://patch.msgid.link/20240919130444.2100447-9-aardelean@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/iio/adc/ad7606.h')
| -rw-r--r-- | drivers/iio/adc/ad7606.h | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 25e84efd15c3..14ee75aa225b 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -63,7 +63,8 @@ struct ad7606_state; -typedef int (*ad7606_scale_setup_cb_t)(struct ad7606_state *st, int ch); +typedef int (*ad7606_scale_setup_cb_t)(struct ad7606_state *st, + struct iio_chan_spec *chan, int ch); /** * struct ad7606_chip_info - chip specific information @@ -94,6 +95,8 @@ struct ad7606_chip_info { * such that it can be read via the 'read_avail' hook * @num_scales number of elements stored in the scale_avail array * @range voltage range selection, selects which scale to apply + * @reg_offset offset for the register value, to be applied when + * writing the value of 'range' to the register value */ struct ad7606_chan_scale { #define AD760X_MAX_SCALES 16 @@ -102,6 +105,7 @@ struct ad7606_chan_scale { int scale_avail_show[AD760X_MAX_SCALE_SHOW]; unsigned int num_scales; unsigned int range; + unsigned int reg_offset; }; /** @@ -158,9 +162,13 @@ struct ad7606_state { /* * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. - * 16 * 16-bit samples + 64-bit timestamp + * 16 * 16-bit samples + 64-bit timestamp - for AD7616 + * 8 * 32-bit samples + 64-bit timestamp - for AD7616C-18 (and similar) */ - unsigned short data[20] __aligned(IIO_DMA_MINALIGN); + union { + u16 buf16[20]; + u32 buf32[10]; + } data __aligned(IIO_DMA_MINALIGN); __be16 d16[2]; }; @@ -201,6 +209,8 @@ enum ad7606_supported_device_ids { ID_AD7606_6, ID_AD7606_4, ID_AD7606B, + ID_AD7606C_16, + ID_AD7606C_18, ID_AD7616, }; |