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| author | Bjorn Helgaas <bhelgaas@google.com> | 2025-10-03 12:13:23 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-10-03 12:13:23 -0500 |
| commit | 30eccd3b7d2f0cdd86929fc9a0f7d75493fb520e (patch) | |
| tree | 5d2c7d1aeccf4fdbb344f4e353678622c8ac33a4 /drivers/pci/controller/dwc/pcie-stm32.h | |
| parent | Merge branch 'pci/controller/sophgo' (diff) | |
| parent | MAINTAINERS: Add entry for ST STM32MP25 PCIe drivers (diff) | |
| download | linux-30eccd3b7d2f0cdd86929fc9a0f7d75493fb520e.tar.gz linux-30eccd3b7d2f0cdd86929fc9a0f7d75493fb520e.zip | |
Merge branch 'pci/controller/stm32'
- Update pinctrl documentation of initial states and use in runtime
suspend/resume (Christian Bruel)
- Add pinctrl_pm_select_init_state() for use by stm32 driver, which needs
it during resume (Christian Bruel)
- Add devicetree bindings and drivers for the STMicroelectronics STM32MP25
in host and endpoint modes (Christian Bruel)
* pci/controller/stm32:
MAINTAINERS: Add entry for ST STM32MP25 PCIe drivers
PCI: stm32-ep: Add PCIe Endpoint support for STM32MP25
dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings
PCI: stm32: Add PCIe host support for STM32MP25
dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings
pinctrl: Add pinctrl_pm_select_init_state helper function
Documentation: pinctrl: Describe PM helper functions for standard states.
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-stm32.h')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-stm32.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-stm32.h b/drivers/pci/controller/dwc/pcie-stm32.h new file mode 100644 index 000000000000..09d39f04e469 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-stm32.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * ST PCIe driver definitions for STM32-MP25 SoC + * + * Copyright (C) 2025 STMicroelectronics - All Rights Reserved + * Author: Christian Bruel <christian.bruel@foss.st.com> + */ + +#define to_stm32_pcie(x) dev_get_drvdata((x)->dev) + +#define STM32MP25_PCIECR_TYPE_MASK GENMASK(11, 8) +#define STM32MP25_PCIECR_EP 0 +#define STM32MP25_PCIECR_LTSSM_EN BIT(2) +#define STM32MP25_PCIECR_RC BIT(10) + +#define SYSCFG_PCIECR 0x6000 |