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| author | Samuel Holland <samuel.holland@sifive.com> | 2025-09-09 15:41:27 -0700 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2025-09-11 19:13:21 +0100 |
| commit | 941327ca5ddd45cfc4dd960cbbabed9e2b5cb1b0 (patch) | |
| tree | 5de5229522d713a39c0d385d2148f28eb2f0f644 /rust/kernel/lib.rs | |
| parent | dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value (diff) | |
| download | linux-941327ca5ddd45cfc4dd960cbbabed9e2b5cb1b0.tar.gz linux-941327ca5ddd45cfc4dd960cbbabed9e2b5cb1b0.zip | |
cache: sifive_ccache: Optimize cache flushes
Fence instructions are required only at the beginning and the end of
a flush operation, not separately for each cache line being flushed.
Speed up cache flushes by about 15% by removing the extra fences.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'rust/kernel/lib.rs')
0 files changed, 0 insertions, 0 deletions