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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2022-09-03 12:30:23 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-09-03 12:30:23 -0700 |
| commit | d958edb9eef115cdd6709face6ab46fefd74324b (patch) | |
| tree | 574c75c06166a8978967d3fd91d6ce608d2fc996 /scripts/generate_rust_analyzer.py | |
| parent | Merge branch 'riscv-variable_fixes_without_kvm' of git://git.kernel.org/pub/s... (diff) | |
| parent | riscv: dts: microchip: use an mpfs specific l2 compatible (diff) | |
| download | linux-d958edb9eef115cdd6709face6ab46fefd74324b.tar.gz linux-d958edb9eef115cdd6709face6ab46fefd74324b.zip | |
Merge tag 'dt-fixes-for-palmer-6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into fixes
Microchip RISC-V devicetree fixes for 6.0-rc4 (or later)
A fix for the warnings introduced in rc3 as part of fixing the console
spam from the L2's isr.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'dt-fixes-for-palmer-6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git:
riscv: dts: microchip: use an mpfs specific l2 compatible
dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions