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| author | Nicolas Ferre <nicolas.ferre@microchip.com> | 2025-08-27 17:08:10 +0200 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@microchip.com> | 2025-09-17 19:15:32 +0200 |
| commit | af98caeaa7b6ad11eb7b7c8bfaddc769df2889f3 (patch) | |
| tree | 4fe13d629b1af0fc2699c664fb95ab976dd31607 /tools/docs/lib/parse_data_structs.py | |
| parent | ARM: at91: pm: save and restore ACR during PLL disable/enable (diff) | |
| download | linux-af98caeaa7b6ad11eb7b7c8bfaddc769df2889f3.tar.gz linux-af98caeaa7b6ad11eb7b7c8bfaddc769df2889f3.zip | |
clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register
This register is important for sequencing the commands to PLLs, so
actually write the update bits with regmap_write_bits() instead of
relying on a read/modify/write regmap command that could skip the actual
hardware write if the value is identical to the one read.
It's changed when modification is needed to the PLL, when
read-only operation is done, we could keep the call to
regmap_update_bits().
Add a comment to the sam9x60_div_pll_set_div() function that uses this
PLL_UPDT register so that it's used consistently, according to the
product's datasheet.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Tested-by: Ryan Wanner <ryan.wanner@microchip.com> # on sama7d65 and sam9x75
Link: https://lore.kernel.org/r/20250827150811.82496-1-nicolas.ferre@microchip.com
[claudiu.beznea: fix "Alignment should match open parenthesis"
checkpatch.pl check]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Diffstat (limited to 'tools/docs/lib/parse_data_structs.py')
0 files changed, 0 insertions, 0 deletions