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| author | Denzeel Oliva <wachiturroxd150@gmail.com> | 2025-08-30 16:28:39 +0000 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-08-31 12:54:00 +0200 |
| commit | ce2eb09b430ddf9d7c9d685bdd81de011bccd4ad (patch) | |
| tree | f6b61645242441ff2dc2f15237908802f9fa9524 /tools/docs/lib/parse_data_structs.py | |
| parent | clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes (diff) | |
| download | linux-ce2eb09b430ddf9d7c9d685bdd81de011bccd4ad.tar.gz linux-ce2eb09b430ddf9d7c9d685bdd81de011bccd4ad.zip | |
clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
Correct several mux/div widths (DSP_BUS, G2D_MSCL, HSI0 USBDP_DEBUG,
HSI1 UFS_EMBD, APM_BUS, CPUCL0_DBG_BUS, DPU) to match hardware.
Fixes: bdd03ebf721f ("clk: samsung: Introduce Exynos990 clock controller driver")
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20250830-fix-cmu-top-v5-2-7c62f608309e@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/docs/lib/parse_data_structs.py')
0 files changed, 0 insertions, 0 deletions