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| author | Imre Deak <imre.deak@intel.com> | 2025-11-17 12:45:39 +0200 |
|---|---|---|
| committer | Mika Kahola <mika.kahola@intel.com> | 2025-11-19 13:24:20 +0200 |
| commit | 5df82b17928b8f14d7167a5e199b4cb58bfe39e1 (patch) | |
| tree | ecee8f40ba5155e8e8865d9a11de30466cfe1847 /tools/lib/python | |
| parent | 230d4c748113d83931a5b57c844fb71faf9eebe3 (diff) | |
| download | linux-5df82b17928b8f14d7167a5e199b4cb58bfe39e1.tar.gz linux-5df82b17928b8f14d7167a5e199b4cb58bfe39e1.zip | |
drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup
Define the C10 PLL SSC register range via macros, so the HW/SW state of
these register can be verified by a follow-up change, reusing these
macros.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-10-mika.kahola@intel.com
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions