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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 12:10:49 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 12:10:49 +0200 |
| commit | 049bddcb893141503923bf0dfc518136269c0a24 (patch) | |
| tree | 56747830f15d77e4dadf62c72d3da2bdc739ceeb /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | clk: renesas: r9a07g044: Fix OSTM1 module clock name (diff) | |
| parent | dt-bindings: clock: Add r9a09g011 CPG Clock Definitions (diff) | |
| download | linux-049bddcb893141503923bf0dfc518136269c0a24.tar.gz linux-049bddcb893141503923bf0dfc518136269c0a24.zip | |
Merge tag 'renesas-r9a09g011-dt-binding-defs-tag' into renesas-clk-for-v5.19
Renesas RZ/V2M DT Binding Definitions
Clock definitions for the Renesas RZ/V2M (R9A09G011) SoC, shared by
driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions