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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-04-28 10:12:22 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-04-28 10:12:22 +0200 |
| commit | 557b7e545e09b8b994aa959ec1a29fc23db0fe0f (patch) | |
| tree | 4b0a1c64bbfe9a2b260669df5c7bce943be0cf40 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | Linux 5.7-rc1 (diff) | |
| parent | clk: renesas: Add r8a7742 CPG Core Clock Definitions (diff) | |
| download | linux-557b7e545e09b8b994aa959ec1a29fc23db0fe0f.tar.gz linux-557b7e545e09b8b994aa959ec1a29fc23db0fe0f.zip | |
Merge tag 'renesas-r8a7742-dt-binding-defs-tag' into renesas-drivers-for-v5.8
Renesas RZ/G1H DT Binding Definitions
Clock and Power Domain definitions for the Renesas RZ/G1H (R8A7742) SoC,
shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
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