diff options
| author | Wanpeng Li <wanpeng.li@hotmail.com> | 2017-10-11 05:10:19 -0700 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2017-10-12 14:01:54 +0200 |
| commit | a554d207dc46b205dcd707888ba31b13c7cfc009 (patch) | |
| tree | d3ca7a16f7e8e0e9e22567657580b832e90dadfa /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch (diff) | |
| download | linux-a554d207dc46b205dcd707888ba31b13c7cfc009.tar.gz linux-a554d207dc46b205dcd707888ba31b13c7cfc009.zip | |
KVM: X86: Processor States following Reset or INIT
- XCR0 is reset to 1 by RESET but not INIT
- XSS is zeroed by both RESET and INIT
- BNDCFGU, BND0-BND3, BNDCFGS, BNDSTATUS are zeroed by both RESET and INIT
This patch does this according to SDM.
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Jim Mattson <jmattson@google.com>
Signed-off-by: Wanpeng Li <wanpeng.li@hotmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions