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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-29 12:23:34 +0200 |
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| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-29 12:23:34 +0200 |
| commit | d1fcd661ba7fe4d487f2deafe708fd2306e0493f (patch) | |
| tree | e7edb024cbc1101f8b454e14ab0e484c44a44203 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4 (diff) | |
| parent | dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions (diff) | |
| download | linux-d1fcd661ba7fe4d487f2deafe708fd2306e0493f.tar.gz linux-d1fcd661ba7fe4d487f2deafe708fd2306e0493f.zip | |
Merge tag 'renesas-r8a779g0-dt-binding-defs-tag' into renesas-clk-for-v5.19
Renesas R-Car V4H DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car V4H (R8A779G0)
SoC, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
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