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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-05-01 09:34:50 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 12:10:21 +0200 |
| commit | 84c9829d16d86a09703d9f2c8dac3816c56bcdcd (patch) | |
| tree | bee90b248eadf52fb7e100352f997e602f4bb372 /tools/perf/scripts/python/bin | |
| parent | clk: renesas: r9a07g043: Add TSU clock and reset entry (diff) | |
| download | linux-84c9829d16d86a09703d9f2c8dac3816c56bcdcd.tar.gz linux-84c9829d16d86a09703d9f2c8dac3816c56bcdcd.zip | |
clk: renesas: r9a07g043: Add clock and reset entries for ADC
Add clock and reset entries for ADC block in CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions