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| author | Jani Nikula <jani.nikula@intel.com> | 2025-09-12 17:48:41 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2025-09-17 11:27:57 +0300 |
| commit | 7d112811787f03030f301975af4079a1efe7cdcc (patch) | |
| tree | 6245074404cf71dca71e9e69838755fb09969d21 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | c8cf6e3cc27c52cfe42d246e96f6e83266b9a0db (diff) | |
| download | linux-7d112811787f03030f301975af4079a1efe7cdcc.tar.gz linux-7d112811787f03030f301975af4079a1efe7cdcc.zip | |
drm/i915: do cck get/put inside vlv_get_cck_clock()
Move towards VLV/CHV clock interfaces that handle sideband get/put
inside them instead of at the caller.
With this, we can switch to the simpler vlv_punit_get()/vlv_punit_put()
in vlv_get_cdclk().
We'll need to move vlv_init_gpll_ref_freq() outside of the existing
get/put in vlv_rps_init() and chv_rps_init().
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/480b654b6c736a03343dfd17eb130c39fd82c637.1757688216.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions