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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-09-12 16:59:26 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-09-18 16:16:23 +0300 |
| commit | 089b5773c219b9bd5e3c7ac72d6ad933dd050f4d (patch) | |
| tree | 2bcb58a0321b36241a20fcd9bffd0f813e797bc6 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 96e556ef5ced51eec140db4bd89204c9322959cc (diff) | |
| download | linux-089b5773c219b9bd5e3c7ac72d6ad933dd050f4d.tar.gz linux-089b5773c219b9bd5e3c7ac72d6ad933dd050f4d.zip | |
drm/i915: Defeature DRRS on LNL+
DRRS has been defeatured on LNL+. Adjust HAS_DOUBLE_BUFFERED_M_N()
to match.
Note that the M/N registers still appear to be double buffered under
the hood but the double buffer update point is now documented to be
just the last register write to the M/N registers, so it no longer
happens synchronously with the vblank/MSA transmission. We should
perhaps rename HAS_DOUBLE_BUFFERED_M_N() to more accurately reflect
reality, but couldn't come up with a decent name right now...
Bspec: 68917
HSD: 14016007525
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250912135926.18910-1-ville.syrjala@linux.intel.com
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions