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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-09-19 22:29:48 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-09-23 18:08:08 +0300 |
| commit | a1d0a0549d425cb21e2be4b7fd4f76e0379e6f2d (patch) | |
| tree | 6f5c4b2bf399713cd77d5737e5cfe10c6305eec3 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 97fd25f8b6380525dafe4f3b8f7f215ac8560caf (diff) | |
| download | linux-a1d0a0549d425cb21e2be4b7fd4f76e0379e6f2d.tar.gz linux-a1d0a0549d425cb21e2be4b7fd4f76e0379e6f2d.zip | |
drm/i915/dram: Also apply the 16Gb DIMM w/a for larger DRAM chips
While the spec only asks us to do the WM0 latency bump for 16Gb
DRAM devices I believe we should apply it for larger DRAM chips.
At the time the w/a was added there were no larger chips on
the market, but I think I've seen at least 32Gb DDR4 chips
being available these days.
Whether it's possible to actually find suitable DIMMs for the
affected systems with largers chips I don't know. Also it's
not known whether the 1 usec latency bump would be sufficient
for larger chips. Someone would need to find such DIMMs and
test this. Fortunately we do have a bit of extra latency already
with the 1 usec bump, as the actual requirement was .4 usec for
for 16Gb chips.
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250919193000.17665-2-ville.syrjala@linux.intel.com
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