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| author | Curtis Malainey <cujomalainey@chromium.org> | 2019-11-05 17:13:35 -0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-11-11 13:02:06 +0000 |
| commit | ba0b3a977ecf525231d36f2d9f3a6ea05c35090a (patch) | |
| tree | 341e7425717c32d3e09685b9a54b07732efbb925 /tools/perf/scripts/python/stackcollapse.py | |
| parent | ASoC: bdw-rt5677: Turn on MCLK1 for DSP via DAPM (diff) | |
| download | linux-ba0b3a977ecf525231d36f2d9f3a6ea05c35090a.tar.gz linux-ba0b3a977ecf525231d36f2d9f3a6ea05c35090a.zip | |
ASoC: rt5677: Set ADC clock to use PLL and enable ASRC
Use the PLL to kept the correct 24M clock rate so frequency shift does
not occur when using the DSP VAD.
Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20191106011335.223061-11-cujomalainey@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions