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| author | Christian Lamparter <chunkeey@gmail.com> | 2020-08-22 18:19:21 +0200 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2020-08-26 17:03:13 -0700 |
| commit | c4cd6fcae46fd14aed8665b7cf66d0954765a873 (patch) | |
| tree | 668d97bc7c65704720687ce6dca6a0c3d292f6ba /tools/perf/scripts/python/stackcollapse.py | |
| parent | ARM: dts: BCM5301X: Specify uart2 in the DT (diff) | |
| download | linux-c4cd6fcae46fd14aed8665b7cf66d0954765a873.tar.gz linux-c4cd6fcae46fd14aed8665b7cf66d0954765a873.zip | |
ARM: dts: BCM5301X: Specify pcie2 in the DT
The SoC supports three pcie ports. Currently, only
pcie0 and pcie1 are enabled. This patch adds the
pcie2 port as well.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions