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| author | LinCheng Ku <lincheng.ku@amd.com> | 2025-12-03 10:18:16 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-12-16 13:25:25 -0500 |
| commit | cea573a8e1ed83840a2173d153dd68e172849d44 (patch) | |
| tree | 4bed1f7439710295aec218565eac2a6806364af8 /tools/perf/scripts/python/stackcollapse.py | |
| parent | db2373ad05d41069f3eb39c6963a131b7fdc9f2b (diff) | |
| download | linux-cea573a8e1ed83840a2173d153dd68e172849d44.tar.gz linux-cea573a8e1ed83840a2173d153dd68e172849d44.zip | |
drm/amd/display: Add USB-C DP Alt Mode lane limitation in DCN32
[Why]
USB-C DisplayPort Alt Mode with concurrent USB data needs lane count
limitation to prevent incorrect 4-lane DP configuration when only 2 lanes
are available due to hardware lane sharing between DP and USB3.
[How]
Query DMUB for Alt Mode status (is_dp_alt_disable, is_usb, is_dp4) in
dcn32_link_encoder_get_max_link_cap() and cap DP to 2 lanes when USB is
active on USB-C port. Added inline documentation explaining the USB-C
lane sharing constraint.
Reviewed-by: PeiChen Huang <peichen.huang@amd.com>
Signed-off-by: LinCheng Ku <lincheng.ku@amd.com>
Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions