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| author | Robert Richter <rrichter@amd.com> | 2023-06-22 15:55:06 -0500 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-06-25 11:51:17 -0700 |
| commit | d8bffff2016f7aef1c1dbe01125720475507b6f2 (patch) | |
| tree | 99ad0c127a83637e1a3fac1dd151fbcb3be231e9 /tools/perf/scripts/python/stackcollapse.py | |
| parent | cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port (diff) | |
| download | linux-d8bffff2016f7aef1c1dbe01125720475507b6f2.tar.gz linux-d8bffff2016f7aef1c1dbe01125720475507b6f2.zip | |
cxl/port: Remove Component Register base address from struct cxl_dport
The Component Register base address @component_reg_phys is no longer
used after the rework of the Component Register setup which now uses
struct member @comp_map instead. Remove the base address.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230622205523.85375-11-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions