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| author | Johnson Wang <johnson.wang@mediatek.com> | 2022-11-21 20:29:57 +0800 |
|---|---|---|
| committer | Chen-Yu Tsai <wenst@chromium.org> | 2022-11-29 14:43:07 +0800 |
| commit | 633e34d0f46ed36f1de15ede00e4b31f4d7cccae (patch) | |
| tree | 4777fb34e31d2031aff442a3d6a6552fe928c24a /tools/perf/scripts/python | |
| parent | clk: mediatek: Add new clock driver to handle FHCTL hardware (diff) | |
| download | linux-633e34d0f46ed36f1de15ede00e4b31f4d7cccae.tar.gz linux-633e34d0f46ed36f1de15ede00e4b31f4d7cccae.zip | |
clk: mediatek: Change PLL register API for MT8186
Use mtk_clk_register_pllfhs() to enhance frequency hopping and
spread spectrum clocking control for MT8186.
Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221121122957.21611-5-johnson.wang@mediatek.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions