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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2019-01-22 22:57:38 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-01-25 11:26:22 +0100 |
| commit | 8cb8f16c62e5ea9c77ca7d25af761f4eaea670ba (patch) | |
| tree | 29a6cc3bc674c877c31655b9577e61336f77a00c /tools/perf/scripts/python | |
| parent | clk: renesas: r8a774c0: Correct parent clock of DU (diff) | |
| download | linux-8cb8f16c62e5ea9c77ca7d25af761f4eaea670ba.tar.gz linux-8cb8f16c62e5ea9c77ca7d25af761f4eaea670ba.zip | |
clk: renesas: rcar-gen3: Factor out cpg_reg_modify()
There's quite often repeated sequence of a CPG register read-modify-write,
so it seems worth factoring it out into a function -- this saves 68 bytes
of the object code (AArch64 gcc 4.8.5) and simplifies protecting all such
sequences with a spinlock in the next patch...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions